587 lines
17 KiB
C
587 lines
17 KiB
C
/*
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* Copyright (c) 1997-1998, 2000-2002, 2004, 2006-2008, 2011-2015 Wind River
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*Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of Wind River Systems nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* @brief Intel IO APIC/xAPIC driver
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*
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* This module is a driver for the IO APIC/xAPIC (Advanced Programmable
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* Interrupt Controller) for P6 (PentiumPro, II, III) family processors
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* and P7 (Pentium4) family processors. The IO APIC/xAPIC is included
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* in the Intel's system chip set, such as ICH2. Software intervention
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* may be required to enable the IO APIC/xAPIC in some chip sets.
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* The 8259A interrupt controller is intended for use in a uni-processor
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* system, IO APIC can be used in either a uni-processor or multi-processor
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* system. The IO APIC handles interrupts very differently than the 8259A.
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* Briefly, these differences are:
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* - Method of Interrupt Transmission. The IO APIC transmits interrupts
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* through a 3-wire bus and interrupts are handled without the need for
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* the processor to run an interrupt acknowledge cycle.
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* - Interrupt Priority. The priority of interrupts in the IO APIC is
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* independent of the interrupt number. For example, interrupt 10 can
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* be given a higher priority than interrupt 3.
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* - More Interrupts. The IO APIC supports a total of 24 interrupts.
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*
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* The IO APIC unit consists of a set of interrupt input signals, a 24-entry
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* by 64-bit Interrupt Redirection Table, programmable registers, and a message
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* unit for sending and receiving APIC messages over the APIC bus or the
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* Front-Side (system) bus. IO devices inject interrupts into the system by
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* asserting one of the interrupt lines to the IO APIC. The IO APIC selects the
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* corresponding entry in the Redirection Table and uses the information in that
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* entry to format an interrupt request message. Each entry in the Redirection
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* Table can be individually programmed to indicate edge/level sensitive interrupt
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* signals, the interrupt vector and priority, the destination processor, and how
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* the processor is selected (statically and dynamically). The information in
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* the table is used to transmit a message to other APIC units (via the APIC bus
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* or the Front-Side (system) bus). IO APIC is used in the Symmetric IO Mode.
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* The base address of IO APIC is determined in loapic_init() and stored in the
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* global variable ioApicBase and ioApicData.
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* The lower 32 bit value of the redirection table entries for IRQ 0
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* to 15 are edge triggered positive high, and for IRQ 16 to 23 are level
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* triggered positive low.
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*
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* This implementation doesn't support multiple IO APICs.
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*
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* INCLUDE FILES: ioapic.h loapic.h
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*
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*/
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#include <nanokernel.h>
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#include <arch/cpu.h>
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#include "board.h"
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#include <toolchain.h>
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#include <sections.h>
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#include <drivers/ioapic.h> /* public API declarations */
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#include <drivers/loapic.h> /* public API declarations and registers */
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/* IO APIC direct register offsets */
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#define IOAPIC_IND 0x00 /* Index Register */
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#define IOAPIC_DATA 0x10 /* IO window (data) - pc.h */
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#define IOAPIC_IRQPA 0x20 /* IRQ Pin Assertion Register */
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#define IOAPIC_EOI 0x40 /* EOI Register */
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#ifdef IOAPIC_MSI_REDIRECT
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/* direct addressing of the RTEs; including the "configuration register" */
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#define IOAPIC_RTE0_LOW 0x1000
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#define IOAPIC_RTE0_HIGH 0x1004
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#define IOAPIC_RTE0_CONFIG 0x1008
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#define IOAPIC_RTE1_LOW 0x1010
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#define IOAPIC_RTE1_HIGH 0x1014
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#define IOAPIC_RTE1_CONFIG 0x1018
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#define IOAPIC_RTE2_LOW 0x1020
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#define IOAPIC_RTE2_HIGH 0x1024
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#define IOAPIC_RTE2_CONFIG 0x1028
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/*
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* etc., etc. until IOAPIC_RTE63_LOW/IOAPIC_RTE63_HIGH/IOAPIC_RTE63_CONFIG
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*
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* rteLowOffset = IOAPIC_RTE0_LOW + (irq * 0x10)
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* rteHighOffset = IOAPIC_RTE0_HIGH + (irq * 0x10)
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* rteConfigOffset = IOAPIC_RTE0_CONFIG + (irq * 0x10)
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*/
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/*
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* An extention to the "standard" IOAPIC design supports a redirection
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* capability that allows each RTE to specify which of the 8 "redirection
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* registers" to use for determining the MSI address.
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*/
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#define IOAPIC_REDIR_ADDR0 0x2000 /* Dummy entry; reads return all 0's */
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#define IOAPIC_REDIR_ADDR1 0x2004 /* MSI redirection selection reg 1 */
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#define IOAPIC_REDIR_ADDR2 0x2008 /* MSI redirection selection reg 2 */
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#define IOAPIC_REDIR_ADDR3 0x200c /* MSI redirection selection reg 3 */
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#define IOAPIC_REDIR_ADDR4 0x2010 /* MSI redirection selection reg 4 */
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#define IOAPIC_REDIR_ADDR5 0x2014 /* MSI redirection selection reg 5 */
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#define IOAPIC_REDIR_ADDR6 0x2018 /* MSI redirection selection reg 6 */
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#define IOAPIC_REDIR_ADDR7 0x201c /* MSI redirection selection reg 7 */
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/* interrupt status for line interrupts generated via RTE0 through RTE31 */
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#define IOAPIC_LINE_INT_STAT0 0x2040
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/* interrupt status for line interrupts generated via RTE32 through RTE64 */
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#define IOAPIC_LINE_INT_STAT1 0x2044
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/* interrupt mask for line interrupts generated via RTE0 to RTE31 */
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#define IOAPIC_LINE_INT_MASK0 0x2048
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/* interrupt mask for line interrupts generated via RTE32 to RTE63 */
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#define IOAPIC_LINE_INT_MASK1 0x204c
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#endif /* IOAPIC_MSI_REDIRECT */
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/* IO APIC indirect register offset */
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#define IOAPIC_ID 0x00 /* IOAPIC ID */
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#define IOAPIC_VERS 0x01 /* IOAPIC Version */
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#define IOAPIC_ARB 0x02 /* IOAPIC Arbitration ID */
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#define IOAPIC_BOOT 0x03 /* IOAPIC Boot Configuration */
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#define IOAPIC_REDTBL 0x10 /* Redirection Table (24 * 64bit) */
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/* Interrupt delivery type */
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#define IOAPIC_DT_APIC 0x0 /* APIC serial bus */
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#define IOAPIC_DT_FS 0x1 /* Front side bus message*/
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/* Version register bits */
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#define IOAPIC_MRE_MASK 0x00ff0000 /* Max Red. entry mask */
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#define IOAPIC_PRQ 0x00008000 /* this has IRQ reg */
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#define IOAPIC_VERSION 0x000000ff /* version number */
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/* Redirection table entry number */
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#define MAX_REDTABLE_ENTRIES 24
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/* Redirection table entry bits: upper 32 bit */
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#define IOAPIC_DESTINATION 0xff000000
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/* Redirection table entry bits: lower 32 bit */
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#define IOAPIC_VEC_MASK 0x000000ff
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#ifdef IOAPIC_MSI_REDIRECT
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/* RTE configuration register bits */
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#define IOAPIC_RTE_CONFIG_REDIR_SEL 0x7
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#define IOAPIC_RTE_CONFIG_LI0EN 0x8
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#define IOAPIC_RTE_CONFIG_LI1EN 0x10
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#define IOAPIC_RTE_CONFIG_LI2EN 0x20
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#define IOAPIC_RTE_CONFIG_BYPASS_MSI_DISABLE 0x40
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#define IOAPIC_RTE_CONFIG_DISABLE_INT_EXT 0x80
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#endif /* IOAPIC_MSI_REDIRECT */
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#ifndef XIOAPIC_DIRECT_ADDRESSING
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static uint32_t __IoApicGet(int32_t offset);
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static void __IoApicSet(int32_t offset, uint32_t value);
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#endif
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static void ioApicRedSetHi(unsigned int irq, uint32_t upper32);
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static void ioApicRedSetLo(unsigned int irq, uint32_t lower32);
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static uint32_t ioApicRedGetLo(unsigned int irq);
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static void _IoApicRedUpdateLo(unsigned int irq, uint32_t value,
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uint32_t mask);
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/*
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* The functions irq_enable() and irq_disable() are implemented in the
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* interrupt controller driver due to the IRQ virtualization imposed by
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* the x86 architecture.
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*/
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/**
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*
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* @brief Initialize the IO APIC or xAPIC
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*
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* This routine initializes the IO APIC or xAPIC.
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*
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* @return N/A
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*/
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void _ioapic_init(void)
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{
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int32_t ix; /* redirection table index */
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uint32_t rteValue; /* value to copy into redirection table entry */
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#ifdef IOAPIC_MSI_REDIRECT
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_IoApicRedirRegSet(MSI_REDIRECT_SELECT_ID, MSI_REDIRECT_TARGET_ADDR);
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#endif
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/*
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* The platform must set the Kconfig option IOAPIC_NUM_RTES to indicate
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* the number of redirection table entries supported by the IOAPIC.
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*
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* Note: The number of actual IRQs supported by the IOAPIC can be
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* determined at runtime by computing:
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*
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* ((__IoApicGet(IOAPIC_VERS) & IOAPIC_MRE_MASK) >> 16) + 1
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*/
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/*
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* Initialize the redirection table entries with default settings;
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* actual interrupt vectors are specified during irq_connect().
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*
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* A future enhancement should make this initialization "table driven":
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* use data provided by the platform to specify the initial state
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*/
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rteValue = IOAPIC_EDGE | IOAPIC_HIGH | IOAPIC_FIXED | IOAPIC_INT_MASK |
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IOAPIC_PHYSICAL | 0 /* dummy vector */;
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for (ix = 0; ix < CONFIG_IOAPIC_NUM_RTES; ix++) {
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ioApicRedSetHi(ix, 0);
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ioApicRedSetLo(ix, rteValue);
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}
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}
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/**
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*
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* @brief Send EOI (End Of Interrupt) signal to IO APIC
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*
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* This routine sends an EOI signal to the IO APIC's interrupting source.
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* @param irq Interrupt number to send EOI
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*
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* @return N/A
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*/
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void _ioapic_eoi(unsigned int irq)
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{
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*(volatile unsigned int *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_EOI) = irq;
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*(volatile unsigned int *)(CONFIG_LOAPIC_BASE_ADDRESS + LOAPIC_EOI) = 0;
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}
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/**
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*
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* @brief Get EOI (End Of Interrupt) information
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*
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* This routine returns EOI signalling information for a specific IRQ.
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*
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* @param irq IRQ number of interest
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* @param argRequired Pointer to "argument required" result area
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* @param arg Pointer to "argument value" result area
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* @return address of routine to be called to signal EOI;
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* as a side effect, also passes back indication if routine requires
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* an interrupt vector argument and what the argument value should be
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*/
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void *_ioapic_eoi_get(unsigned int irq, char *argRequired, void **arg)
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{
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#ifndef XIOAPIC_DIRECT_ADDRESSING
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if (!(__IoApicGet(IOAPIC_VERS) & IOAPIC_PRQ)) {
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*argRequired = 0;
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return _loapic_eoi;
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}
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#endif
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/* indicate that an argument to the EOI handler is required */
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*argRequired = 1;
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/*
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* The parameter to the ioApicIntEoi() routine is the vector programmed
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* into the redirection table. The interrupt controller's
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* _SysIntVecAlloc() routine must invoke _IoApicIntEoiGet() after
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* _IoApicRedVecSet() to ensure the redirection table contains the desired
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* interrupt vector.
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*/
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*arg = (void *)(ioApicRedGetLo(irq) & IOAPIC_VEC_MASK);
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return _ioapic_eoi;
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}
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/**
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*
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* @brief Enable a specified APIC interrupt input line
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*
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* This routine enables a specified APIC interrupt input line.
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* @param irq IRQ number to enable
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*
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* @return N/A
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*/
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void _ioapic_irq_enable(unsigned int irq)
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{
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_IoApicRedUpdateLo(irq, 0, IOAPIC_INT_MASK);
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}
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/**
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*
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* @brief Disable a specified APIC interrupt input line
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*
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* This routine disables a specified APIC interrupt input line.
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* @param irq IRQ number to disable
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*
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* @return N/A
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*/
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void _ioapic_irq_disable(unsigned int irq)
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{
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_IoApicRedUpdateLo(irq, IOAPIC_INT_MASK, IOAPIC_INT_MASK);
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}
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/**
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*
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* @brief Programs the interrupt redirection table
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*
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* This routine sets up the redirection table entry for the specified IRQ
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* @param irq Virtualized IRQ
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* @param vector Vector number
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* @param flags Interrupt flags
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*
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* @return N/A
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*/
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void _ioapic_irq_set(unsigned int irq, unsigned int vector, uint32_t flags)
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{
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uint32_t rteValue; /* value to copy into redirection table entry */
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rteValue = IOAPIC_FIXED | IOAPIC_INT_MASK | IOAPIC_PHYSICAL |
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(vector & IOAPIC_VEC_MASK) | flags;
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ioApicRedSetHi(irq, 0);
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ioApicRedSetLo(irq, rteValue);
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}
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/**
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*
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* @brief Program interrupt vector for specified irq
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*
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* The routine writes the interrupt vector in the Interrupt Redirection
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* Table for specified irq number
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*
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* @param irq Interrupt number
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* @param vector Vector number
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* @return N/A
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*/
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void _ioapic_int_vec_set(unsigned int irq, unsigned int vector)
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{
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_IoApicRedUpdateLo(irq, vector, IOAPIC_VEC_MASK);
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}
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#ifndef XIOAPIC_DIRECT_ADDRESSING
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/**
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*
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* @brief Read a 32 bit IO APIC register
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*
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* This routine reads the specified IO APIC register using indirect addressing.
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* @param offset Register offset (8 bits)
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*
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* @return register value
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*/
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static uint32_t __IoApicGet(int32_t offset)
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{
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uint32_t value; /* value */
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int key; /* interrupt lock level */
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/* lock interrupts to ensure indirect addressing works "atomically" */
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key = irq_lock();
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*((volatile char *)
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(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_IND)) = (char)offset;
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value = *((volatile uint32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA));
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irq_unlock(key);
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return value;
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}
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/**
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*
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* @brief Write a 32 bit IO APIC register
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*
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* This routine writes the specified IO APIC register using indirect addressing.
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*
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* @param offset Register offset (8 bits)
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* @param value Value to set the register
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* @return N/A
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*/
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static void __IoApicSet(int32_t offset, uint32_t value)
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{
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int key; /* interrupt lock level */
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/* lock interrupts to ensure indirect addressing works "atomically" */
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key = irq_lock();
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*(volatile char *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_IND) = (char)offset;
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*((volatile uint32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + IOAPIC_DATA)) = value;
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irq_unlock(key);
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}
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#endif
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/**
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*
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* @brief Get low 32 bits of Redirection Table entry
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*
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* This routine reads the low-order 32 bits of a Redirection Table entry.
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*
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* @param irq INTIN number
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* @return 32 low-order bits
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*/
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static uint32_t ioApicRedGetLo(unsigned int irq)
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{
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#ifdef XIOAPIC_DIRECT_ADDRESSING
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volatile uint32_t *pEntry; /* pointer to redirection table entry */
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pEntry = (volatile uint32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + (irq * 0x10) +
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IOAPIC_RTE0_LOW);
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return *pEntry;
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#else
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int32_t offset = IOAPIC_REDTBL + (irq << 1); /* register offset */
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return __IoApicGet(offset);
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#endif
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}
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/**
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*
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* @brief Set low 32 bits of Redirection Table entry
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*
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* This routine writes the low-order 32 bits of a Redirection Table entry.
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*
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* @param irq INTIN number
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* @param lower32 Value to be written
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* @return N/A
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*/
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static void ioApicRedSetLo(unsigned int irq, uint32_t lower32)
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{
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#ifdef XIOAPIC_DIRECT_ADDRESSING
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volatile uint32_t *pEntry; /* pointer to redirection table entry */
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pEntry = (volatile uint32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + (irq * 0x10) +
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IOAPIC_RTE0_LOW);
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*pEntry = lower32;
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#else
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int32_t offset = IOAPIC_REDTBL + (irq << 1); /* register offset */
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__IoApicSet(offset, lower32);
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#endif
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}
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/**
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*
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* @brief Set high 32 bits of Redirection Table entry
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*
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* This routine writes the high-order 32 bits of a Redirection Table entry.
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*
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* @param irq INTIN number
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* @param upper32 Value to be written
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* @return N/A
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*/
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static void ioApicRedSetHi(unsigned int irq, uint32_t upper32)
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{
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#ifdef XIOAPIC_DIRECT_ADDRESSING
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volatile uint32_t *pEntry; /* pointer to redirection table entry */
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pEntry = (volatile uint32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + (irq * 0x10) +
|
|
IOAPIC_RTE0_HIGH);
|
|
|
|
*pEntry = upper32;
|
|
#else
|
|
int32_t offset = IOAPIC_REDTBL + (irq << 1) + 1; /* register offset */
|
|
|
|
__IoApicSet(offset, upper32);
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
*
|
|
* @brief Modify low 32 bits of Redirection Table entry
|
|
*
|
|
* This routine modifies selected portions of the low-order 32 bits of a
|
|
* Redirection Table entry, as indicated by the associate bit mask.
|
|
*
|
|
* @param irq INTIN number
|
|
* @param value Value to be written
|
|
* @param mask Mask of bits to be modified
|
|
* @return N/A
|
|
*/
|
|
static void _IoApicRedUpdateLo(unsigned int irq,
|
|
uint32_t value,
|
|
uint32_t mask)
|
|
{
|
|
ioApicRedSetLo(irq, (ioApicRedGetLo(irq) & ~mask) | (value & mask));
|
|
}
|
|
|
|
#ifdef IOAPIC_MSI_REDIRECT
|
|
|
|
/*
|
|
* The platform is responsible for defining the IOAPIC_MSI_REDIRECT
|
|
* macro if the I/O APIC supports the MSI redirect capability.
|
|
*/
|
|
|
|
/**
|
|
*
|
|
* @brief Write to the RTE config register for specified IRQ
|
|
*
|
|
* This routine writes the specified 32-bit <value> into the RTE configuration
|
|
* register for the specified <irq> (0 to (CONFIG_IOAPIC_NUM_RTES - 1))
|
|
*
|
|
* @param irq INTIN number
|
|
* @param value Value to be written
|
|
* @return N/A
|
|
*/
|
|
static void _IoApicRteConfigSet(unsigned int irq, uint32_t value)
|
|
{
|
|
unsigned int offset; /* register offset */
|
|
|
|
#ifdef CONFIG_IOAPIC_DEBUG
|
|
if (irq >= CONFIG_IOAPIC_NUM_RTES)
|
|
return; /* do nothing if <irq> is invalid */
|
|
#endif
|
|
|
|
offset = IOAPIC_RTE0_CONFIG + (irq * 0x10);
|
|
|
|
/* use direct addressing when writing to RTE config register */
|
|
|
|
*((volatile uint32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + offset)) = value;
|
|
}
|
|
|
|
/**
|
|
*
|
|
* @brief Write to the specified MSI redirection register
|
|
*
|
|
* This routine writes the 32-bit <value> into the redirection register
|
|
* specified by <reg>.
|
|
* @param reg Register
|
|
* @param value Value to be written
|
|
*
|
|
* @return N/A
|
|
*/
|
|
static void _IoApicRedirRegSet(unsigned int reg, uint32_t value)
|
|
{
|
|
unsigned int offset; /* register offset */
|
|
|
|
#ifdef CONFIG_IOAPIC_DEBUG
|
|
if ((reg > 7) || (reg == 0))
|
|
return; /* do nothing if <reg> is invalid */
|
|
#endif
|
|
|
|
offset = IOAPIC_REDIR_ADDR0 + (reg * 4);
|
|
|
|
/* use direct addressing when writing to RTE config register */
|
|
|
|
*((volatile uint32_t *)(CONFIG_IOAPIC_BASE_ADDRESS + offset)) = value;
|
|
}
|
|
|
|
#endif /* IOAPIC_MSI_REDIRECT */
|