366 lines
10 KiB
C
366 lines
10 KiB
C
/*
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* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ite_it8xxx2_timer
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#include <drivers/timer/system_timer.h>
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#include <dt-bindings/interrupt-controller/ite-intc.h>
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#include <soc.h>
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#include <spinlock.h>
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#include <sys_clock.h>
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#include <logging/log.h>
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LOG_MODULE_REGISTER(timer, LOG_LEVEL_ERR);
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/* Control external timer3~8 */
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#define IT8XXX2_EXT_TIMER_BASE (DT_INST_REG_ADDR(0))/*0x00F01F10*/
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#define IT8XXX2_EXT_CTRLX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + (n << 3))
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#define IT8XXX2_EXT_PSRX(n) ECREG(IT8XXX2_EXT_TIMER_BASE + 0x01 + (n << 3))
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#define IT8XXX2_EXT_CNTX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x04 + \
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(n << 3))
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#define IT8XXX2_EXT_CNTOX(n) ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x38 + \
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(n << 2))
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/* Event timer configurations */
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#define EVENT_TIMER EXT_TIMER_3
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#define EVENT_TIMER_IRQ DT_INST_IRQ_BY_IDX(0, 0, irq)
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#define EVENT_TIMER_FLAG DT_INST_IRQ_BY_IDX(0, 0, flags)
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/* Event timer max count is 512 sec (base on clock source 32768Hz) */
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#define EVENT_TIMER_MAX_CNT 0x00FFFFFFUL
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/* Free run timer configurations */
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#define FREE_RUN_TIMER EXT_TIMER_4
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#define FREE_RUN_TIMER_IRQ DT_INST_IRQ_BY_IDX(0, 1, irq)
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#define FREE_RUN_TIMER_FLAG DT_INST_IRQ_BY_IDX(0, 1, flags)
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/* Free run timer max count is 36.4 hr (base on clock source 32768Hz) */
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#define FREE_RUN_TIMER_MAX_CNT 0xFFFFFFFFUL
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#ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
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/*
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* One shot timer configurations
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*
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* NOTE: Timer1/2 register address isn't regular like timer3/4/5/6/7/8, and
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* timer1 is used for printing watchdog warning message. So now we use
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* timer2 only one shot to wake up chip and change pll.
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*/
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#define WDT_BASE DT_REG_ADDR(DT_NODELABEL(twd0))
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#define WDT_REG (struct wdt_it8xxx2_regs *)(WDT_BASE)
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#define ONE_SHOT_TIMER_IRQ DT_IRQ_BY_IDX(DT_NODELABEL(twd0), 1, irq)
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#define ONE_SHOT_TIMER_FLAG DT_IRQ_BY_IDX(DT_NODELABEL(twd0), 1, flags)
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#endif
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#define MS_TO_COUNT(hz, ms) ((hz) * (ms) / 1000)
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/*
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* One system (kernel) tick is as how much HW timer counts
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*
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* NOTE: Event and free run timer individually select the same clock source
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* frequency, so they can use the same HW_CNT_PER_SYS_TICK to tranform
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* unit between HW count and system tick. If clock source frequency is
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* different, then we should define another to tranform.
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*/
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#define HW_CNT_PER_SYS_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \
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/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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/* Event timer max count is as how much system (kernal) tick */
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#define EVEN_TIMER_MAX_CNT_SYS_TICK (EVENT_TIMER_MAX_CNT \
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/ HW_CNT_PER_SYS_TICK)
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enum ext_clk_src_sel {
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EXT_PSR_32P768K = 0,
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EXT_PSR_1P024K,
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EXT_PSR_32,
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EXT_PSR_8M,
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};
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/*
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* 24-bit timers: external timer 3, 5, and 7
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* 32-bit timers: external timer 4, 6, and 8
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*/
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enum ext_timer_idx {
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EXT_TIMER_3 = 0, /* Event timer */
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EXT_TIMER_4, /* Free run timer */
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EXT_TIMER_5,
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EXT_TIMER_6,
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EXT_TIMER_7,
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EXT_TIMER_8,
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};
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static struct k_spinlock lock;
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/* Last HW count that we called sys_clock_announce() */
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static volatile uint32_t last_announced_hw_cnt;
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#ifdef CONFIG_SOC_IT8XXX2_PLL_FLASH_48M
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static void timer_5ms_one_shot_isr(const void *unused)
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{
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ARG_UNUSED(unused);
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/*
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* We are here because we have completed changing PLL sequence,
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* so disabled one shot timer interrupt.
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*/
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irq_disable(ONE_SHOT_TIMER_IRQ);
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}
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/*
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* This timer is used to wake up chip from sleep mode to complete
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* changing PLL sequence.
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*/
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void timer_5ms_one_shot(void)
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{
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struct wdt_it8xxx2_regs *const timer2_reg = WDT_REG;
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uint32_t hw_cnt;
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/* Initialize interrupt handler of one shot timer */
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IRQ_CONNECT(ONE_SHOT_TIMER_IRQ, 0, timer_5ms_one_shot_isr, NULL,
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ONE_SHOT_TIMER_FLAG);
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/* Set rising edge triggered of one shot timer */
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ite_intc_irq_priority_set(ONE_SHOT_TIMER_IRQ, 0, ONE_SHOT_TIMER_FLAG);
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/* Clear interrupt status of one shot timer */
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ite_intc_isr_clear(ONE_SHOT_TIMER_IRQ);
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/* Set clock source of one shot timer */
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timer2_reg->ET2PSR = EXT_PSR_32P768K;
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/*
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* Set count of one shot timer,
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* and after write ET2CNTLLR timer will start
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*/
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hw_cnt = MS_TO_COUNT(32768, 5/*ms*/);
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timer2_reg->ET2CNTLH2R = (uint8_t)((hw_cnt >> 16) & 0xff);
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timer2_reg->ET2CNTLHR = (uint8_t)((hw_cnt >> 8) & 0xff);
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timer2_reg->ET2CNTLLR = (uint8_t)(hw_cnt & 0xff);
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irq_enable(ONE_SHOT_TIMER_IRQ);
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}
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#endif /* CONFIG_SOC_IT8XXX2_PLL_FLASH_48M */
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static void evt_timer_isr(const void *unused)
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{
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ARG_UNUSED(unused);
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/* Disable event timer */
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IT8XXX2_EXT_CTRLX(EVENT_TIMER) &= ~IT8XXX2_EXT_ETXEN;
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/* W/C event timer interrupt status */
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ite_intc_isr_clear(EVENT_TIMER_IRQ);
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if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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/*
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* Get free run observer count from last time announced and
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* trnaform unit to system tick
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*/
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uint32_t dticks = (~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER)) -
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last_announced_hw_cnt) / HW_CNT_PER_SYS_TICK;
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last_announced_hw_cnt += (dticks * HW_CNT_PER_SYS_TICK);
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sys_clock_announce(dticks);
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} else {
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/* Enable and re-start event timer */
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IT8XXX2_EXT_CTRLX(EVENT_TIMER) |= (IT8XXX2_EXT_ETXEN |
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IT8XXX2_EXT_ETXRST);
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/* Informs kernel that one system tick has elapsed */
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sys_clock_announce(1);
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}
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}
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void sys_clock_set_timeout(int32_t ticks, bool idle)
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{
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uint32_t hw_cnt;
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ARG_UNUSED(idle);
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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/* Always return for non-tickless kernel system */
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return;
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}
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/* Critical section */
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k_spinlock_key_t key = k_spin_lock(&lock);
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/* NOTE: To reduce cpu effort, we don't add critical section here */
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if (ticks == K_TICKS_FOREVER) {
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hw_cnt = EVENT_TIMER_MAX_CNT;
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} else if (ticks <= 1) {
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/*
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* Ticks <= 1 means the kernel wants the tick announced
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* as soon as possible, ideally no more than one system tick
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* in the future. So set event timer count to 1 system tick or
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* at least 1 hw count.
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*/
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hw_cnt = MAX((1 * HW_CNT_PER_SYS_TICK), 1);
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} else {
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if (ticks > EVEN_TIMER_MAX_CNT_SYS_TICK)
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/*
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* Set event timer count to EVENT_TIMER_MAX_CNT, after
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* interrupt fired the remaining time will be set again
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* by sys_clock_announce().
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*/
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hw_cnt = EVENT_TIMER_MAX_CNT;
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else
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/*
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* Set event timer count to system tick or at least
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* 1 hw count
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*/
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hw_cnt = MAX((ticks * HW_CNT_PER_SYS_TICK), 1);
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}
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/* Set event timer 24-bit count */
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IT8XXX2_EXT_CNTX(EVENT_TIMER) = hw_cnt;
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/* Enable and re-start event timer */
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IT8XXX2_EXT_CTRLX(EVENT_TIMER) |= (IT8XXX2_EXT_ETXEN |
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IT8XXX2_EXT_ETXRST);
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/* W/C event timer interrupt status */
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ite_intc_isr_clear(EVENT_TIMER_IRQ);
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k_spin_unlock(&lock, key);
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LOG_DBG("timeout is 0x%x, set hw count 0x%x", ticks, hw_cnt);
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}
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uint32_t sys_clock_elapsed(void)
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{
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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/* Always return 0 for non-tickless kernel system */
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return 0;
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}
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/* Critical section */
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k_spinlock_key_t key = k_spin_lock(&lock);
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/*
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* Get free run observer count from last time announced and trnaform
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* unit to system tick
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*/
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uint32_t dticks = (~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER)) -
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last_announced_hw_cnt) / HW_CNT_PER_SYS_TICK;
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k_spin_unlock(&lock, key);
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return dticks;
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}
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uint32_t sys_clock_cycle_get_32(void)
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{
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/*
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* Get free run observer count and trnaform unit to system tick
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*
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* NOTE: Timer is counting down from 0xffffffff. In not combined
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* mode, the observer count value is the same as count, so after
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* NOT count operation we can get counting up value; In
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* combined mode, the observer count value is the same as NOT
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* count operation.
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*/
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uint32_t dticks = (~(IT8XXX2_EXT_CNTOX(FREE_RUN_TIMER)))
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/ HW_CNT_PER_SYS_TICK;
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return dticks;
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}
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static int timer_init(enum ext_timer_idx ext_timer,
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enum ext_clk_src_sel clock_source_sel,
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uint32_t raw,
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uint32_t ms,
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uint8_t first_time_enable,
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uint32_t irq_num,
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uint32_t irq_flag,
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uint8_t with_int,
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uint8_t start)
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{
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uint32_t hw_cnt;
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if (raw) {
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hw_cnt = ms;
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} else {
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if (clock_source_sel == EXT_PSR_32P768K)
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hw_cnt = MS_TO_COUNT(32768, ms);
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else if (clock_source_sel == EXT_PSR_1P024K)
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hw_cnt = MS_TO_COUNT(1024, ms);
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else if (clock_source_sel == EXT_PSR_32)
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hw_cnt = MS_TO_COUNT(32, ms);
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else if (clock_source_sel == EXT_PSR_8M)
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hw_cnt = 8000 * ms;
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else {
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LOG_ERR("Timer %d clock source error !", ext_timer);
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return -1;
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}
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}
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if (hw_cnt == 0) {
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LOG_ERR("Timer %d count shouldn't be 0 !", ext_timer);
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return -1;
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}
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if (first_time_enable) {
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/* Enable and re-start external timer x */
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IT8XXX2_EXT_CTRLX(ext_timer) |= (IT8XXX2_EXT_ETXEN |
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IT8XXX2_EXT_ETXRST);
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/* Disable external timer x */
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IT8XXX2_EXT_CTRLX(ext_timer) &= ~IT8XXX2_EXT_ETXEN;
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}
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/* Set rising edge triggered of external timer x */
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ite_intc_irq_priority_set(irq_num, 0, irq_flag);
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/* Clear interrupt status of external timer x */
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ite_intc_isr_clear(irq_num);
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/* Set clock source of external timer x */
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IT8XXX2_EXT_PSRX(ext_timer) = clock_source_sel;
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/* Set count of external timer x */
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IT8XXX2_EXT_CNTX(ext_timer) = hw_cnt;
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/* Disable external timer x */
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IT8XXX2_EXT_CTRLX(ext_timer) &= ~IT8XXX2_EXT_ETXEN;
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if (start)
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/* Enable and re-start external timer x */
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IT8XXX2_EXT_CTRLX(ext_timer) |= (IT8XXX2_EXT_ETXEN |
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IT8XXX2_EXT_ETXRST);
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if (with_int)
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irq_enable(irq_num);
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else
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irq_disable(irq_num);
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return 0;
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}
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int sys_clock_driver_init(const struct device *dev)
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{
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int ret;
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ARG_UNUSED(dev);
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/* Set 32-bit timer4 for free run*/
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ret = timer_init(FREE_RUN_TIMER, EXT_PSR_32P768K, TRUE,
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FREE_RUN_TIMER_MAX_CNT, TRUE, FREE_RUN_TIMER_IRQ,
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FREE_RUN_TIMER_FLAG, FALSE, TRUE);
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if (ret < 0) {
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LOG_ERR("Init free run timer failed");
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return ret;
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}
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/* Set 24-bit timer3 for timeout event */
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IRQ_CONNECT(EVENT_TIMER_IRQ, 0, evt_timer_isr, NULL, EVENT_TIMER_FLAG);
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if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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ret = timer_init(EVENT_TIMER, EXT_PSR_32P768K, TRUE,
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EVENT_TIMER_MAX_CNT, TRUE, EVENT_TIMER_IRQ,
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EVENT_TIMER_FLAG, TRUE, FALSE);
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} else {
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/* Start a event timer in one system tick */
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ret = timer_init(EVENT_TIMER, EXT_PSR_32P768K, TRUE,
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MAX((1 * HW_CNT_PER_SYS_TICK), 1), TRUE,
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EVENT_TIMER_IRQ, EVENT_TIMER_FLAG,
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TRUE, TRUE);
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}
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if (ret < 0) {
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LOG_ERR("Init event timer failed");
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return ret;
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}
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return 0;
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}
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