Michal Sieron 7b601b7f50 dts: riscv: litex-vexriscv: Fix clock node address ... Also change its register indentation from spaces to tabs Signed-off-by: Michal Sieron <msieron@internships.antmicro.com>		2022-05-27 15:27:11 -07:00
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andes	dts: riscv: andes: Move SoC devicetree includes under a vendor directory	2022-05-09 17:54:48 -04:00
espressif	esp32/s2/c3: pinctrl: dts: move pinctrl node out of SoC bus	2022-05-13 11:25:58 -07:00
gigadevice	dts: migrate includes to <zephyr/...>	2022-05-06 19:54:54 +02:00
ite	dts: riscv: ite: Move SoC devicetree includes under a vendor directory	2022-05-09 17:54:48 -04:00
microsemi	dts: riscv: microsemi: Move SoC devicetree includes under a vendor dir	2022-05-09 17:54:48 -04:00
openisa	dts: riscv: openisa: Move SoC devicetree includes under a vendor dir	2022-05-09 17:54:48 -04:00
sifive	dts: riscv: sifive: Move SoC devicetree includes under a vendor dir	2022-05-09 17:54:48 -04:00
starfive	dts: migrate includes to <zephyr/...>	2022-05-06 19:54:54 +02:00
telink	dts: riscv: telink: Move SoC devicetree includes under a vendor dir	2022-05-09 17:54:48 -04:00
mpfs-icicle.dtsi	dts: riscv: introduce Polarfire SOC QSPI interface	2022-05-06 11:32:54 +02:00
neorv32.dtsi	dts: migrate includes to <zephyr/...>	2022-05-06 19:54:54 +02:00
riscv32-litex-vexriscv.dtsi	dts: riscv: litex-vexriscv: Fix clock node address	2022-05-27 15:27:11 -07:00
virt.dtsi	…