82 lines
2.0 KiB
Plaintext
82 lines
2.0 KiB
Plaintext
/*
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* Copyright (c) 2021 Electrolance Solutions
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <st/h7/stm32h7.dtsi>
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#include <zephyr/dt-bindings/display/stm32_ltdc.h>
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/ {
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soc {
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flash-controller@52002000 {
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flash0: flash@8000000 {
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write-block-size = <16>;
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erase-block-size = <DT_SIZE_K(8)>;
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};
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};
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dmamux1: dmamux@40020800 {
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dma-requests= <111>;
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};
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ltdc: display-controller@50001000 {
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compatible = "st,stm32-ltdc";
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reg = <0x50001000 0x200>;
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interrupts = <88 0>, <89 0>;
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interrupt-names = "ltdc", "ltdc_er";
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clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00000008>;
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label = "LTDC";
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status = "disabled";
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};
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};
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/* System data RAM accessible over AXI bus: AXI SRAM1 in CD domain */
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sram0: memory@24000000 {
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compatible = "mmio-sram";
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reg = <0x24000000 DT_SIZE_K(256)>;
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};
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/* System data RAM accessible over AXI bus: AXI SRAM2 in CD domain */
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sram1: memory@24040000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x24040000 DT_SIZE_K(384)>;
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zephyr,memory-region = "SRAM1";
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};
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/* System data RAM accessible over AXI bus: AXI SRAM3 in CD domain */
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sram2: memory@240A0000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x240A0000 DT_SIZE_K(384)>;
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zephyr,memory-region = "SRAM2";
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};
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/* System data RAM accessible over AHB bus: SRAM1 in CD domain */
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sram3: memory@30000000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x30000000 DT_SIZE_K(64)>;
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zephyr,memory-region = "SRAM3";
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};
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/* System data RAM accessible over AHB bus: SRAM2 in CD domain */
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sram4: memory@30010000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x30010000 DT_SIZE_K(64)>;
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zephyr,memory-region = "SRAM4";
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};
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/* System data RAM accessible over AHB bus: SRD SRAM in SRD domain */
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sram5: memory@38000000 {
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x38000000 DT_SIZE_K(32)>;
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zephyr,memory-region = "SRAM5";
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};
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dtcm: memory@20000000 {
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compatible = "zephyr,memory-region", "arm,dtcm";
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reg = <0x20000000 DT_SIZE_K(128)>;
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zephyr,memory-region = "DTCM";
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};
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};
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