zephyr/boards/riscv/qemu_riscv32
Carlo Caione 10061efdc4 riscv: Rework and cleanup Kconfig
This patch is doing several things:

- Core ISA and extension Kconfig symbols have now a formalized name
  (CONFIG_RISCV_ISA_* and CONFIG_RISCV_ISA_EXT_*)

- a new Kconfig.isa file was introduced with the full set of extensions
  currently supported by the v2.2 spec

- a new Kconfig.core file was introduced to host all the RISCV cores
  (currently only E31)

- ISA and extensions settings are moved to SoC configuration files

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2022-06-05 14:28:42 +02:00
..
doc
Kconfig.board riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00
Kconfig.defconfig riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00
board.cmake
qemu_riscv32.dts
qemu_riscv32.yaml
qemu_riscv32_defconfig
qemu_riscv32_smp.dts
qemu_riscv32_smp.yaml
qemu_riscv32_smp_defconfig
qemu_riscv32_xip-pinctrl.dtsi boards: migrate includes to <zephyr/...> 2022-05-06 19:57:15 +02:00
qemu_riscv32_xip.dts dts: riscv: sifive: Move SoC devicetree includes under a vendor dir 2022-05-09 17:54:48 -04:00
qemu_riscv32_xip.yaml
qemu_riscv32_xip_defconfig riscv: Rework and cleanup Kconfig 2022-06-05 14:28:42 +02:00