508 lines
14 KiB
Plaintext
508 lines
14 KiB
Plaintext
# x86 general configuration options
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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# SPDX-License-Identifier: Apache-2.0
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menu "X86 Architecture Options"
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depends on X86
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config ARCH
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default "x86"
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#
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# CPU Families - the SoC configuration should select the right one.
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#
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config CPU_ATOM
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bool
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select CPU_HAS_FPU
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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select X86_CPU_HAS_MMX
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select X86_CPU_HAS_SSE
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select X86_CPU_HAS_SSE2
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select X86_CPU_HAS_SSE3
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help
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This option signifies the use of a CPU from the Atom family.
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config CPU_APOLLO_LAKE
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bool
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select CPU_HAS_FPU
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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select X86_MMU
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select X86_CPU_HAS_MMX
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select X86_CPU_HAS_SSE
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select X86_CPU_HAS_SSE2
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select X86_CPU_HAS_SSE3
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select X86_CPU_HAS_SSSE3
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select X86_CPU_HAS_SSE41
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select X86_CPU_HAS_SSE42
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help
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This option signifies the use of a CPU from the Apollo Lake family.
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config CPU_LAKEMONT
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bool
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select CPU_HAS_FPU
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select ARCH_HAS_STACK_PROTECTION if X86_MMU
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select ARCH_HAS_USERSPACE if X86_MMU
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select X86_CPU_HAS_MMX
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select X86_CPU_HAS_SSE
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select X86_CPU_HAS_SSE2
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select X86_CPU_HAS_SSE3
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select X86_CPU_HAS_SSSE3
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help
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This option signifies the use of a CPU from the Lakemont family.
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#
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# Configuration common to both IA32 and Intel64 sub-architectures.
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#
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config X86_64
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bool "Run in 64-bit mode"
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select 64BIT
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select USE_SWITCH
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select USE_SWITCH_SUPPORTED
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select SCHED_IPI_SUPPORTED
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select X86_MMU
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select X86_CPU_HAS_MMX
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select X86_CPU_HAS_SSE
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select X86_CPU_HAS_SSE2
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select X86_MMX
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select X86_SSE
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select X86_SSE2
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menu "x86 Features"
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config X86_CPU_HAS_MMX
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bool
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config X86_CPU_HAS_SSE
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bool
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config X86_CPU_HAS_SSE2
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bool
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config X86_CPU_HAS_SSE3
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bool
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config X86_CPU_HAS_SSSE3
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bool
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config X86_CPU_HAS_SSE41
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bool
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config X86_CPU_HAS_SSE42
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bool
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config X86_CPU_HAS_SSE4A
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bool
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if FPU || X86_64
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config X86_MMX
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bool "MMX Support"
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depends on X86_CPU_HAS_MMX
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help
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This option enables MMX support, and the use of MMX registers
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by threads.
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config X86_SSE
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bool "SSE Support"
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depends on X86_CPU_HAS_SSE
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help
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This option enables SSE support, and the use of SSE registers
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by threads.
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config X86_SSE2
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bool "SSE2 Support"
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depends on X86_CPU_HAS_SSE2
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select X86_SSE
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help
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This option enables SSE2 support.
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config X86_SSE3
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bool "SSE3 Support"
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depends on X86_CPU_HAS_SSE3
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select X86_SSE
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help
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This option enables SSE3 support.
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config X86_SSSE3
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bool "SSSE3 (Supplemental SSE3) Support"
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depends on X86_CPU_HAS_SSSE3
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select X86_SSE
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help
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This option enables Supplemental SSE3 support.
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config X86_SSE41
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bool "SSE4.1 Support"
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depends on X86_CPU_HAS_SSE41
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select X86_SSE
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help
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This option enables SSE4.1 support.
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config X86_SSE42
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bool "SSE4.2 Support"
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depends on X86_CPU_HAS_SSE42
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select X86_SSE
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help
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This option enables SSE4.2 support.
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config X86_SSE4A
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bool "SSE4A Support"
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depends on X86_CPU_HAS_SSE4A
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select X86_SSE
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help
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This option enables SSE4A support.
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config X86_SSE_FP_MATH
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bool "Compiler-generated SSEx instructions for floating point math"
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depends on X86_SSE
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help
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This option allows the compiler to generate SSEx instructions for
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performing floating point math. This can greatly improve performance
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when exactly the same operations are to be performed on multiple
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data objects; however, it can also significantly reduce performance
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when preemptive task switches occur because of the larger register
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set that must be saved and restored.
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Disabling this option means that the compiler utilizes only the
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x87 instruction set for floating point operations.
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endif # FPU || X86_64
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endmenu
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config SRAM_OFFSET
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default 0x100000 if X86_PC_COMPATIBLE
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help
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A lot of x86 that resemble PCs have many reserved physical memory
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regions within the first megabyte. Specify an offset from the
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beginning of RAM to load the kernel in physical memory, avoiding these
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regions.
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Note that this does not include the "locore" which contains real mode
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bootstrap code within the first 64K of physical memory.
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This value normally need to be page-aligned.
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config KERNEL_VM_OFFSET
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default 0x100000 if MMU
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config MAX_IRQ_LINES
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int "Number of IRQ lines"
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default 128
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range 0 224
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help
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This option specifies the number of IRQ lines in the system. It
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determines the size of the _irq_to_interrupt_vector_table, which
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is used to track the association between vectors and IRQ numbers.
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config IRQ_OFFLOAD_VECTOR
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int "IDT vector to use for IRQ offload"
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default 33
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range 32 255
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depends on IRQ_OFFLOAD
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config PIC_DISABLE
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bool "Disable PIC"
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help
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This option disables all interrupts on the legacy i8259 PICs at boot.
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choice
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prompt "Reboot implementation"
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depends on REBOOT
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default REBOOT_RST_CNT
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config REBOOT_RST_CNT
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bool "Reboot via RST_CNT register"
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help
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Reboot via the RST_CNT register, going back to BIOS.
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endchoice
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config ACPI
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bool "ACPI (Advanced Configuration and Power Interface) support"
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depends on X86_PC_COMPATIBLE
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help
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Allow retrieval of platform configuration at runtime.
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config PCIE_MMIO_CFG
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bool "Use MMIO PCI configuration space access"
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select ACPI
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help
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Selects the use of the memory-mapped PCI Express Extended
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Configuration Space instead of the traditional 0xCF8/0xCFC
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IO Port registers.
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config KERNEL_VM_SIZE
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default 0x40000000 if ACPI
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config X86_PC_COMPATIBLE
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bool
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default y
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select ARCH_HAS_RESERVED_PAGE_FRAMES
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select HAS_SRAM_OFFSET
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help
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Hidden option to signal building for PC-compatible platforms
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with BIOS, ACPI, etc.
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config X86_MEMMAP
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bool "Use memory map"
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select ARCH_HAS_RESERVED_PAGE_FRAMES
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help
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Enable the use of memory map to identify regions of memory.
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The memory map can be populated via Multiboot
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(CONFIG_MULTIBOOT=y and CONFIG_MULTIBOOT_MEMMAP=y) or
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can be manually defined via x86_memmap[].
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config X86_MEMMAP_ENTRIES
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int "Number of memory map entries"
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depends on X86_MEMMAP
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range 1 256
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default 1 if !MULTIBOOT_MEMMAP
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default 64 if MULTIBOOT_MEMMAP
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help
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Maximum number of memory regions to hold in the memory map.
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config MULTIBOOT
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bool "Generate multiboot header"
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depends on X86_PC_COMPATIBLE
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default y
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help
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Embed a multiboot header in the output executable. This is used
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by some boot loaders (e.g., GRUB) when loading Zephyr. It is safe
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to leave this option on if you're not sure. It only expands the
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text segment by 12-16 bytes and is typically ignored if not needed.
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if MULTIBOOT
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config MULTIBOOT_INFO
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bool "Preserve multiboot information structure"
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help
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Multiboot passes a pointer to an information structure to the
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kernel entry point. Some drivers (e.g., the multiboot framebuffer
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display driver) need to refer to information in this structure,
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and so set this option to preserve the data in a permanent location.
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config MULTIBOOT_MEMMAP
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bool "Use multiboot memory map if provided"
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select MULTIBOOT_INFO
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select X86_MEMMAP
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help
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Use the multiboot memory map if the loader provides one.
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config MULTIBOOT_FRAMEBUF
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bool "Multiboot framebuffer support"
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select DISPLAY
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select FRAMEBUF_DISPLAY
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select MULTIBOOT_INFO
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if MULTIBOOT_FRAMEBUF
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config MULTIBOOT_FRAMEBUF_X
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int "Multiboot framebuffer X pixels"
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default 640
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config MULTIBOOT_FRAMEBUF_Y
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int "Multiboot framebuffer Y pixels"
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default 480
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endif # MULTIBOOT_FRAMEBUF
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endif # MULTIBOOT
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config EXCEPTION_DEBUG
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bool "Unhandled exception debugging"
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default y
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depends on LOG
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help
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Install handlers for various CPU exception/trap vectors to
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make debugging them easier, at a small expense in code size.
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This prints out the specific exception vector and any associated
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error codes.
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config X86_VERY_EARLY_CONSOLE
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bool "Support very early boot printk"
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depends on PRINTK
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help
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Non-emulated X86 devices often require special hardware to attach
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a debugger, which may not be easily available. This option adds a
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very minimal serial driver which gets initialized at the very
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beginning of z_cstart(), via arch_kernel_init(). This driver enables
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printk to emit messages to the 16550 UART port 0 instance in device
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tree. This mini-driver assumes I/O to the UART is done via ports.
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config X86_MMU
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bool "Memory Management Unit"
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select MMU
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help
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This options enables the memory management unit present in x86
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and creates a set of page tables at boot time that is runtime-
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mutable.
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config X86_COMMON_PAGE_TABLE
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bool "Use a single page table for all threads"
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default n
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depends on USERSPACE
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depends on !SMP
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depends on !X86_KPTI
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help
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If this option is enabled, userspace memory domains will not have their
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own page tables. Instead, context switching operations will modify
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page tables in place. This is much slower, but uses much less RAM
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for page tables.
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config X86_MAX_ADDITIONAL_MEM_DOMAINS
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int "Maximum number of memory domains"
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default 3
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depends on X86_MMU && USERSPACE && !X86_COMMON_PAGE_TABLE
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help
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The initial page tables at boot are pre-allocated, and used for the
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default memory domain. Instantiation of additional memory domains
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if common page tables are in use requires a pool of free pinned
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memory pages for constructing page tables.
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Zephyr test cases assume 3 additional domains can be instantiated.
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config X86_EXTRA_PAGE_TABLE_PAGES
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int "Reserve extra pages in page table"
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default 1 if X86_PAE && (KERNEL_VM_BASE != SRAM_BASE_ADDRESS)
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default 0
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depends on X86_MMU
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help
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The whole page table is pre-allocated at build time and is
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dependent on the range of address space. This allows reserving
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extra pages (of size CONFIG_MMU_PAGE_SIZE) to the page table
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so that gen_mmu.py can make use of these extra pages.
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Says 0 unless absolutely sure that this is necessary.
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config X86_NO_MELTDOWN
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC is not vulnerable to the Meltdown CPU vulnerability,
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as described in CVE-2017-5754.
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config X86_NO_SPECTRE_V1
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC is not vulnerable to the Spectre V1, V1.1, V1.2, and
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swapgs CPU vulnerabilities as described in CVE-2017-5753,
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CVE-2018-3693, and CVE-2019-1125.
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config X86_NO_SPECTRE_V2
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC is not vulnerable to the Spectre V2 CPU
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vulnerability, as described in CVE-2017-5715.
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config X86_NO_SPECTRE_V4
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC is not vulnerable to the Spectre V4 CPU
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vulnerability, as described in CVE-2018-3639.
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config X86_NO_LAZY_FP
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bool
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help
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This hidden option should be set on a per-SOC basis to indicate
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that a particular SOC is not vulnerable to the Lazy FP CPU
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vulnerability, as described in CVE-2018-3665.
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config X86_NO_SPECULATIVE_VULNERABILITIES
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bool
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select X86_NO_MELTDOWN
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select X86_NO_SPECTRE_V1
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select X86_NO_SPECTRE_V2
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select X86_NO_SPECTRE_V4
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select X86_NO_LAZY_FP
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help
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This hidden option should be set on a per-SOC basis to indicate that
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a particular SOC does not perform any kind of speculative execution,
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or is a newer chip which is immune to the class of vulnerabilities
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which exploit speculative execution side channel attacks.
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config DISABLE_SSBD
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bool "Disable Speculative Store Bypass"
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depends on USERSPACE
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default y if !X86_NO_SPECTRE_V4
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help
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This option will disable Speculative Store Bypass in order to
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mitigate against certain kinds of side channel attacks. Quoting
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the "Speculative Execution Side Channels" document, version 2.0:
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When SSBD is set, loads will not execute speculatively
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until the addresses of all older stores are known. This
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ensure s that a load does not speculatively consume stale
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data values due to bypassing an older store on the same
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logical processor.
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If enabled, this applies to all threads in the system.
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Even if enabled, will have no effect on CPUs that do not
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require this feature.
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config ENABLE_EXTENDED_IBRS
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bool "Extended IBRS"
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depends on USERSPACE
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default y if !X86_NO_SPECTRE_V2
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help
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This option will enable the Extended Indirect Branch Restricted
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Speculation 'always on' feature. This mitigates Indirect Branch
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Control vulnerabilities (aka Spectre V2).
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config X86_BOUNDS_CHECK_BYPASS_MITIGATION
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bool
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depends on USERSPACE
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default y if !X86_NO_SPECTRE_V1
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select BOUNDS_CHECK_BYPASS_MITIGATION
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help
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Hidden config to select arch-independent option to enable
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Spectre V1 mitigations by default if the CPU is not known
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to be immune to it.
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config X86_KPTI
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bool "Kernel page table isolation"
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default y
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depends on USERSPACE
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depends on !X86_NO_MELTDOWN
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help
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Implements kernel page table isolation to mitigate Meltdown exploits
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to read Kernel RAM. Incurs a significant performance cost for
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user thread interrupts and system calls, and significant footprint
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increase for additional page tables and trampoline stacks.
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config X86_EFI
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bool "EFI"
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default y
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depends on BUILD_OUTPUT_EFI
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help
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Enable EFI support. This means you build your image with zefi
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support. See arch/x86/zefi/README.txt for more information.
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config X86_EFI_CONSOLE
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bool
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depends on X86_EFI && X86_64 && !X86_VERY_EARLY_CONSOLE
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default y
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help
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This enables the use of the UEFI console device as the
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Zephyr printk handler. It requires that no interferences
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with hardware used by the firmware console (e.g. a UART or
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framebuffer) happens from Zephyr code, and that all memory
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used by the firmware environment and its page tables be
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separate and preserved. In general this is safe to assume,
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but no automatic checking exists at runtime to verify.
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Likewise be sure to disable any other console/printk
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drivers!
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source "arch/x86/core/Kconfig.ia32"
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source "arch/x86/core/Kconfig.intel64"
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endmenu
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