zephyr/soc/xtensa/sample_controller
Daniel Leung 307708c450 xtensa: sample_controller: smaller intermediate build artifacts
For some weird reasons, if the sections in linker script are not
in memory address order, there are lots of padding involved in
zephyr_pre0.elf. This moves the .intList section to its memory
ordered location. When building hello_world, this shrinks
zephyr_pre0.elf from 512MB to 339KB.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-08-22 10:00:46 +02:00
..
include
CMakeLists.txt
Kconfig.defconfig
Kconfig.soc
linker.ld