191 lines
7.0 KiB
C
191 lines
7.0 KiB
C
/*
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* Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT kvaser_pcican
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#include "can_sja1000.h"
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#include <zephyr/drivers/can.h>
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#include <zephyr/drivers/pcie/pcie.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/sys/util.h>
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LOG_MODULE_REGISTER(can_kvaser_pci, CONFIG_CAN_LOG_LEVEL);
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/* AMCC S5920 I/O BAR registers */
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#define S5920_INTCSR_REG 0x38
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#define S5920_INTCSR_ADDINT_EN BIT(13)
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#define S5920_PTCR_REG 0x60
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/* Xilinx I/O BAR registers */
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#define XLNX_VERINT_REG 0x07
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#define XLNX_VERINT_VERSION_POS 4U
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struct can_kvaser_pci_config {
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void (*irq_config_func)(const struct device *dev);
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struct pcie_dev *pcie;
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};
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struct can_kvaser_pci_data {
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io_port_t sja1000_base;
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};
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static uint8_t can_kvaser_pci_read_reg(const struct device *dev, uint8_t reg)
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{
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struct can_sja1000_data *sja1000_data = dev->data;
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struct can_kvaser_pci_data *kvaser_data = sja1000_data->custom;
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io_port_t addr = kvaser_data->sja1000_base + reg;
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return sys_in8(addr);
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}
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static void can_kvaser_pci_write_reg(const struct device *dev, uint8_t reg, uint8_t val)
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{
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struct can_sja1000_data *sja1000_data = dev->data;
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struct can_kvaser_pci_data *kvaser_data = sja1000_data->custom;
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io_port_t addr = kvaser_data->sja1000_base + reg;
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sys_out8(val, addr);
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}
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static int can_kvaser_pci_get_core_clock(const struct device *dev, uint32_t *rate)
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{
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ARG_UNUSED(dev);
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/* The internal clock operates at half of the oscillator frequency */
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*rate = MHZ(16) / 2;
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return 0;
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}
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static int can_kvaser_pci_init(const struct device *dev)
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{
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const struct can_sja1000_config *sja1000_config = dev->config;
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const struct can_kvaser_pci_config *kvaser_config = sja1000_config->custom;
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struct can_sja1000_data *sja1000_data = dev->data;
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struct can_kvaser_pci_data *kvaser_data = sja1000_data->custom;
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struct pcie_bar iobar;
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static io_port_t amcc_base;
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static io_port_t xlnx_base;
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uint32_t intcsr;
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int err;
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if (kvaser_config->pcie->bdf == PCIE_BDF_NONE) {
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LOG_ERR("failed to find PCIe device");
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return -ENODEV;
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}
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pcie_set_cmd(kvaser_config->pcie->bdf, PCIE_CONF_CMDSTAT_IO, true);
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/* AMCC S5920 registers */
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if (!pcie_probe_iobar(kvaser_config->pcie->bdf, 0, &iobar)) {
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LOG_ERR("failed to probe AMCC S5920 I/O BAR");
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return -ENODEV;
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}
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amcc_base = iobar.phys_addr;
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/* SJA1000 registers */
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if (!pcie_probe_iobar(kvaser_config->pcie->bdf, 1, &iobar)) {
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LOG_ERR("failed to probe SJA1000 I/O BAR");
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return -ENODEV;
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}
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kvaser_data->sja1000_base = iobar.phys_addr;
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/* Xilinx registers */
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if (!pcie_probe_iobar(kvaser_config->pcie->bdf, 2, &iobar)) {
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LOG_ERR("failed to probe Xilinx I/O BAR");
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return -ENODEV;
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}
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xlnx_base = iobar.phys_addr;
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LOG_DBG("Xilinx version: %d",
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sys_in8(xlnx_base + XLNX_VERINT_REG) >> XLNX_VERINT_VERSION_POS);
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/*
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* Initialization sequence as per Kvaser PCIcan Hardware Reference Manual (UG 98048
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* v3.0.0).
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*/
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/* AMCC S5920 PCI Pass-Thru Configuration Register (PTCR) */
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sys_out32(0x80808080UL, amcc_base + S5920_PTCR_REG);
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/* AMCC S5920 PCI Interrupt Control/Status Register (INTCSR) */
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intcsr = sys_in32(amcc_base + S5920_INTCSR_REG);
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intcsr |= S5920_INTCSR_ADDINT_EN;
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sys_out32(intcsr, amcc_base + S5920_INTCSR_REG);
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err = can_sja1000_init(dev);
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if (err != 0) {
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LOG_ERR("failed to initialize controller (err %d)", err);
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return err;
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}
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kvaser_config->irq_config_func(dev);
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return 0;
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}
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const struct can_driver_api can_kvaser_pci_driver_api = {
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.get_capabilities = can_sja1000_get_capabilities,
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.start = can_sja1000_start,
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.stop = can_sja1000_stop,
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.set_mode = can_sja1000_set_mode,
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.set_timing = can_sja1000_set_timing,
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.send = can_sja1000_send,
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.add_rx_filter = can_sja1000_add_rx_filter,
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.remove_rx_filter = can_sja1000_remove_rx_filter,
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.get_state = can_sja1000_get_state,
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.set_state_change_callback = can_sja1000_set_state_change_callback,
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.get_core_clock = can_kvaser_pci_get_core_clock,
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.get_max_filters = can_sja1000_get_max_filters,
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.get_max_bitrate = can_sja1000_get_max_bitrate,
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#ifndef CONFIG_CAN_AUTO_BUS_OFF_RECOVERY
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.recover = can_sja1000_recover,
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#endif /* !CONFIG_CAN_AUTO_BUS_OFF_RECOVERY */
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.timing_min = CAN_SJA1000_TIMING_MIN_INITIALIZER,
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.timing_max = CAN_SJA1000_TIMING_MAX_INITIALIZER,
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};
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#define CAN_KVASER_PCI_OCR \
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(CAN_SJA1000_OCR_OCMODE_NORMAL | CAN_SJA1000_OCR_OCTN0 | CAN_SJA1000_OCR_OCTP0 | \
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CAN_SJA1000_OCR_OCTN1 | CAN_SJA1000_OCR_OCTP1)
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#define CAN_KVASER_PCI_CDR (CAN_SJA1000_CDR_CD_DIV2 | CAN_SJA1000_CDR_CLOCK_OFF)
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#define CAN_KVASER_PCI_INIT(inst) \
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static void can_kvaser_pci_config_func_##inst(const struct device *dev); \
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DEVICE_PCIE_INST_DECLARE(inst); \
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\
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static const struct can_kvaser_pci_config can_kvaser_pci_config_##inst = { \
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DEVICE_PCIE_INST_INIT(inst, pcie), \
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.irq_config_func = can_kvaser_pci_config_func_##inst \
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}; \
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\
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static const struct can_sja1000_config can_sja1000_config_##inst = \
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CAN_SJA1000_DT_CONFIG_INST_GET(inst, &can_kvaser_pci_config_##inst, \
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can_kvaser_pci_read_reg, can_kvaser_pci_write_reg, \
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CAN_KVASER_PCI_OCR, CAN_KVASER_PCI_CDR); \
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\
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static struct can_kvaser_pci_data can_kvaser_pci_data_##inst; \
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\
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static struct can_sja1000_data can_sja1000_data_##inst = \
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CAN_SJA1000_DATA_INITIALIZER(&can_kvaser_pci_data_##inst); \
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\
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DEVICE_DT_INST_DEFINE(inst, can_kvaser_pci_init, NULL, &can_sja1000_data_##inst, \
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&can_sja1000_config_##inst, POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
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&can_kvaser_pci_driver_api); \
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\
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static void can_kvaser_pci_config_func_##inst(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), can_sja1000_isr, \
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DEVICE_DT_INST_GET(inst), DT_INST_IRQ(inst, sense)); \
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irq_enable(DT_INST_IRQN(inst)); \
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}
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DT_INST_FOREACH_STATUS_OKAY(CAN_KVASER_PCI_INIT)
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