190 lines
4.2 KiB
Plaintext
190 lines
4.2 KiB
Plaintext
# Kconfig.intel - Intel SPI driver configuration options
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#
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#
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# Copyright (c) 2015-2016 Intel Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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menuconfig SPI_INTEL
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bool
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prompt "Intel SPI controller driver"
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depends on SPI && CPU_MINUTEIA
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default n
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help
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Enable support for Intel's SPI controllers. Such controller
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was formelly found on XScale chips. It can be found nowadays
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on CEXXXX Intel media controller and Quark CPU (2 of them).
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if SPI_INTEL
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choice
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depends on SPI_INTEL
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prompt "Intel SPI interrupt trigger condition"
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default SPI_INTEL_RISING_EDGE
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config SPI_INTEL_FALLING_EDGE
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bool "Falling edge"
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help
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"Intel SPI uses falling edge interrupt"
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config SPI_INTEL_RISING_EDGE
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bool "Rising edge"
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help
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"Intel SPI uses rising edge interrupt"
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config SPI_INTEL_LEVEL_HIGH
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bool "Level high"
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help
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"Intel SPI uses level high interrupt"
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config SPI_INTEL_LEVEL_LOW
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bool "Level low"
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help
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"Intel SPI uses level low interrupt"
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endchoice
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config SPI_INTEL_VENDOR_ID
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hex "PCI Vendor ID"
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depends on SPI_INTEL && PCI
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default 0x8086
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config SPI_INTEL_DEVICE_ID
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hex "PCI Device ID"
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depends on SPI_INTEL && PCI
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default 0x935
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config SPI_INTEL_CLASS
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hex "PCI class"
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depends on SPI_INTEL && PCI
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default 0x0C
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config SPI_INTEL_CS_GPIO
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bool "SPI port CS pin is controlled via a GPIO port"
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depends on SPI_INTEL && GPIO
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default n
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config SPI_INTEL_INIT_PRIORITY
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int
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prompt "Init priority"
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depends on SPI_INTEL
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default 60
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help
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Device driver initialization priority.
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config SPI_INTEL_PORT_0
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bool
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prompt "Intel SPI port 0"
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depends on SPI_INTEL
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default n
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help
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Enable Intel's SPI controller port 0.
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config SPI_INTEL_PORT_0_DRV_NAME
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string
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prompt "Intel SPI port 0 device name"
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depends on SPI_INTEL_PORT_0
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default "SPI_0"
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config SPI_INTEL_PORT_0_BUS
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int "Port 0 PCI Bus"
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depends on SPI_INTEL_PORT_0 && PCI
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config SPI_INTEL_PORT_0_DEV
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int "Port 0 PCI Dev"
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depends on SPI_INTEL_PORT_0 && PCI
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config SPI_INTEL_PORT_0_FUNCTION
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int "Port 0 PCI function"
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depends on SPI_INTEL_PORT_0 && PCI
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config SPI_INTEL_PORT_0_REGS
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hex
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prompt "Port 0 registers address"
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depends on SPI_INTEL_PORT_0
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config SPI_INTEL_PORT_0_IRQ
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int
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prompt "Port 0 interrupt"
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depends on SPI_INTEL_PORT_0
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config SPI_INTEL_PORT_0_PRI
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int
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prompt "Port 0 interrupt priority"
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depends on SPI_INTEL_PORT_0
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config SPI_INTEL_PORT_0_CS_GPIO_PORT
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string
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prompt "The GPIO port which is used to control CS"
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depends on SPI_INTEL_PORT_0 && SPI_INTEL_CS_GPIO
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default GPIO_DW_0_NAME
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config SPI_INTEL_PORT_0_CS_GPIO_PIN
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int "The GPIO PIN which is used to act as a CS pin"
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depends on SPI_INTEL_PORT_0 && SPI_INTEL_CS_GPIO
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default 0
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config SPI_INTEL_PORT_1
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bool
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prompt "Intel SPI port 1"
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depends on SPI_INTEL
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default n
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help
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Enable Intel's SPI controller port 1.
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config SPI_INTEL_PORT_1_DRV_NAME
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string
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prompt "Intel SPI port 1 device name"
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depends on SPI_INTEL_PORT_1
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default "SPI_1"
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config SPI_INTEL_PORT_1_BUS
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int "Port 1 PCI Bus"
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depends on SPI_INTEL_PORT_1 && PCI
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config SPI_INTEL_PORT_1_DEV
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int "Port 1 PCI Dev"
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depends on SPI_INTEL_PORT_1 && PCI
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config SPI_INTEL_PORT_1_FUNCTION
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int "Port 1 PCI function"
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depends on SPI_INTEL_PORT_1 && PCI
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config SPI_INTEL_PORT_1_REGS
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hex
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prompt "Port 1 registers address"
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depends on SPI_INTEL_PORT_1
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config SPI_INTEL_PORT_1_IRQ
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int
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prompt "Port 1 interrupt"
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depends on SPI_INTEL_PORT_1
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config SPI_INTEL_PORT_1_PRI
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int
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prompt "Port 0 interrupt priority"
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depends on SPI_INTEL_PORT_1
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config SPI_INTEL_PORT_1_CS_GPIO_PORT
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string
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prompt "The GPIO port which is used to control CS"
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depends on SPI_INTEL_PORT_1 && SPI_INTEL_CS_GPIO
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default GPIO_DW_0_NAME
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config SPI_INTEL_PORT_1_CS_GPIO_PIN
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int "The GPIO PIN which is used to act as a CS pin"
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depends on SPI_INTEL_PORT_1 && SPI_INTEL_CS_GPIO
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default 0
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endif # SPI_INTEL
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