180 lines
7.8 KiB
C
180 lines
7.8 KiB
C
/*
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* Copyright (c) 2021, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_ARM_NXP_IMX_RT_POWER_RT11XX_H_
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#define _SOC_ARM_NXP_IMX_RT_POWER_RT11XX_H_
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/*
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* Set point configurations. These are kept in a separate file for readability.
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*/
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#define SP0 0
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#define SP1 1
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#define SP2 2
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#define SP3 3
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#define SP4 4
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#define SP5 5
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#define SP6 6
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#define SP7 7
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#define SP8 8
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#define SP9 9
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#define SP10 10
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#define SP11 11
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#define SP12 12
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#define SP13 13
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#define SP14 14
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#define SP15 15
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/* ================= GPC configuration ==================== */
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#define SET_POINT_COUNT 16
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/*
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* SOC set point mappings
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* This matrix defines what set points are allowed for a given core.
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* For example, when SP2 is requested, SP1 or SP2 are allowed set points
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*/
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#define CPU0_COMPATIBLE_SP_TABLE \
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/* NA, SP1, SP2, SP3, SP0, SP4, SP5, SP6, SP7, SP8, SP9, SP10, SP11, SP12, SP13, SP14, SP15 */ \
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/* SP1*/{{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
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/* SP2 */{ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
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/* SP3 */{ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
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/* SP0 */{ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
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/* SP4 */{ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
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/* SP5 */{ 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
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/* SP6 */{ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
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/* SP7 */{ 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}, \
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/* SP8 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0}, \
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/* SP9 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, \
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/* SP10 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0}, \
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/* SP11 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, \
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/* SP12 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, \
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/* SP13 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, \
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/* SP14 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, \
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/* SP15 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}}
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#define CPU1_COMPATIBLE_SP_TABLE \
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/* NA, SP1, SP2, SP3, SP0, SP4, SP5, SP6, SP7, SP8, SP9, SP10, SP11, SP12, SP13, SP14, SP15 */ \
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/* SP1*/{{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
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/* SP2 */{ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
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/* SP3 */{ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0}, \
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/* SP0 */{ 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \
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/* SP4 */{ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0}, \
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/* SP5 */{ 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0}, \
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/* SP6 */{ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0}, \
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/* SP7 */{ 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0}, \
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/* SP8 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0}, \
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/* SP9 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0}, \
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/* SP10 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0}, \
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/* SP11 */{ 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0}, \
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/* SP12 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0}, \
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/* SP13 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0}, \
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/* SP14 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0}, \
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/* SP15 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}}
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/* Allows GPC to control RC16M on/off */
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#define OSC_RC_16M_STBY_VAL 0x0000
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/* ================== DCDC configuration ======================= */
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#define PD_WKUP_SP_VAL 0xf800 /* Off at SP11 - SP 15 */
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#define DCDC_ONOFF_SP_VAL (~PD_WKUP_SP_VAL)
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#define DCDC_DIG_ONOFF_SP_VAL DCDC_ONOFF_SP_VAL
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#define DCDC_LP_MODE_SP_VAL 0x0000
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#define DCDC_ONOFF_STBY_VAL DCDC_ONOFF_SP_VAL
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#define DCDC_LP_MODE_STBY_VAL 0x0000
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/* DCDC 1.8V buck mode target voltage in set points 0-15 */
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#define DCDC_1P8_BUCK_MODE_CONFIGURATION_TABLE \
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{ \
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kDCDC_1P8BuckTarget1P8V, \
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kDCDC_1P8BuckTarget1P8V, \
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kDCDC_1P8BuckTarget1P8V, \
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kDCDC_1P8BuckTarget1P8V, \
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kDCDC_1P8BuckTarget1P8V, \
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kDCDC_1P8BuckTarget1P8V, \
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kDCDC_1P8BuckTarget1P8V, \
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kDCDC_1P8BuckTarget1P8V, \
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kDCDC_1P8BuckTarget1P8V, \
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kDCDC_1P8BuckTarget1P8V, \
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kDCDC_1P8BuckTarget1P8V, \
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kDCDC_1P8BuckTarget1P8V, \
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kDCDC_1P8BuckTarget1P8V, \
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kDCDC_1P8BuckTarget1P8V, \
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kDCDC_1P8BuckTarget1P8V, \
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kDCDC_1P8BuckTarget1P8V, \
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}
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/* DCDC 1.0V buck mode target voltage in set points 0-15 */
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#define DCDC_1P0_BUCK_MODE_CONFIGURATION_TABLE \
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{ \
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kDCDC_1P0BuckTarget1P0V, \
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kDCDC_1P0BuckTarget1P1V, \
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kDCDC_1P0BuckTarget1P1V, \
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kDCDC_1P0BuckTarget1P1V, \
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kDCDC_1P0BuckTarget1P0V, \
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kDCDC_1P0BuckTarget0P9V, \
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kDCDC_1P0BuckTarget0P9V, \
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kDCDC_1P0BuckTarget0P9V, \
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kDCDC_1P0BuckTarget0P9V, \
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kDCDC_1P0BuckTarget0P9V, \
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kDCDC_1P0BuckTarget0P8V, \
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kDCDC_1P0BuckTarget0P9V, \
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kDCDC_1P0BuckTarget0P9V, \
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kDCDC_1P0BuckTarget0P9V, \
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kDCDC_1P0BuckTarget0P9V, \
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kDCDC_1P0BuckTarget0P9V, \
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}
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/* DCDC 1.8V standby mode target voltage in set points 0-15 */
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#define DCDC_1P8_STANDBY_MODE_CONFIGURATION_TABLE \
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{ \
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kDCDC_1P8StbyTarget1P8V, \
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kDCDC_1P8StbyTarget1P8V, \
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kDCDC_1P8StbyTarget1P8V, \
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kDCDC_1P8StbyTarget1P8V, \
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kDCDC_1P8StbyTarget1P8V, \
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kDCDC_1P8StbyTarget1P8V, \
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kDCDC_1P8StbyTarget1P8V, \
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kDCDC_1P8StbyTarget1P8V, \
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kDCDC_1P8StbyTarget1P8V, \
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kDCDC_1P8StbyTarget1P8V, \
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kDCDC_1P8StbyTarget1P8V, \
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kDCDC_1P8StbyTarget1P8V, \
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kDCDC_1P8StbyTarget1P8V, \
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kDCDC_1P8StbyTarget1P8V, \
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kDCDC_1P8StbyTarget1P8V, \
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kDCDC_1P8StbyTarget1P8V, \
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}
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/* DCDC 1.0V standby mode target voltage in set points 0-15 */
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#define DCDC_1P0_STANDBY_MODE_CONFIGURATION_TABLE \
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{ \
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kDCDC_1P0StbyTarget1P0V, \
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kDCDC_1P0StbyTarget1P1V, \
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kDCDC_1P0StbyTarget1P1V, \
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kDCDC_1P0StbyTarget1P1V, \
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kDCDC_1P0StbyTarget1P0V, \
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kDCDC_1P0StbyTarget0P9V, \
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kDCDC_1P0StbyTarget0P9V, \
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kDCDC_1P0StbyTarget0P9V, \
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kDCDC_1P0StbyTarget0P9V, \
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kDCDC_1P0StbyTarget0P9V, \
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kDCDC_1P0StbyTarget0P8V, \
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kDCDC_1P0StbyTarget0P9V, \
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kDCDC_1P0StbyTarget0P9V, \
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kDCDC_1P0StbyTarget0P9V, \
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kDCDC_1P0StbyTarget0P9V, \
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kDCDC_1P0StbyTarget0P9V, \
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}
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#endif /* _SOC_ARM_NXP_IMX_RT_POWER_RT11XX_H_ */
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