756 lines
18 KiB
Plaintext
756 lines
18 KiB
Plaintext
# i.MX RT series
|
|
|
|
# Copyright (c) 2017-2021, NXP
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
|
|
choice
|
|
prompt "i.MX RT Selection"
|
|
depends on SOC_SERIES_IMX_RT
|
|
|
|
config SOC_MIMXRT1011
|
|
bool "SOC_MIMXRT1011"
|
|
select SOC_SERIES_IMX_RT10XX
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_12B1MSPS_SAR
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_FLEXSPI
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ENET_PLL
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_EDMA
|
|
select HAS_MCUX_GPC
|
|
select HAS_MCUX_DCDC
|
|
select HAS_MCUX_PMU
|
|
select HAS_MCUX_IOMUXC
|
|
select HAS_SWO
|
|
|
|
config SOC_MIMXRT1015
|
|
bool "SOC_MIMXRT1015"
|
|
select SOC_SERIES_IMX_RT10XX
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_12B1MSPS_SAR
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_FLEXSPI
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ENET_PLL
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_EDMA
|
|
select HAS_MCUX_GPC
|
|
select HAS_MCUX_DCDC
|
|
select HAS_MCUX_PMU
|
|
select HAS_MCUX_IOMUXC
|
|
select HAS_SWO
|
|
|
|
config SOC_MIMXRT1021
|
|
bool "SOC_MIMXRT1021"
|
|
select SOC_SERIES_IMX_RT10XX
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_12B1MSPS_SAR
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_FLEXSPI
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_SEMC
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ENET_PLL
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
select HAS_MCUX_EDMA
|
|
select HAS_MCUX_FLEXCAN
|
|
select HAS_MCUX_PWM
|
|
select HAS_MCUX_GPC
|
|
select HAS_MCUX_DCDC
|
|
select HAS_MCUX_PMU
|
|
select HAS_MCUX_IOMUXC
|
|
select HAS_SWO
|
|
|
|
config SOC_MIMXRT1024
|
|
bool "SOC_MIMXRT1024"
|
|
select SOC_SERIES_IMX_RT10XX
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_12B1MSPS_SAR
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_FLEXSPI
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_SEMC
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ENET_PLL
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
select HAS_MCUX_EDMA
|
|
select HAS_MCUX_FLEXCAN
|
|
select HAS_MCUX_SRC
|
|
select HAS_MCUX_GPC
|
|
select HAS_MCUX_DCDC
|
|
select HAS_MCUX_PMU
|
|
select HAS_MCUX_IOMUXC
|
|
select HAS_SWO
|
|
|
|
config SOC_MIMXRT1051
|
|
bool "SOC_MIMXRT1051"
|
|
select SOC_SERIES_IMX_RT10XX
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_12B1MSPS_SAR
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_FLEXSPI
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_SEMC
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ARM_PLL
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
select HAS_MCUX_CSI
|
|
select HAS_MCUX_EDMA
|
|
select HAS_MCUX_FLEXCAN
|
|
select HAS_MCUX_GPC
|
|
select HAS_MCUX_DCDC
|
|
select HAS_MCUX_PMU
|
|
select HAS_MCUX_IOMUXC
|
|
select HAS_SWO
|
|
|
|
config SOC_MIMXRT1052
|
|
bool "SOC_MIMXRT1052"
|
|
select SOC_SERIES_IMX_RT10XX
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_12B1MSPS_SAR
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_ELCDIF
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_FLEXSPI
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_SEMC
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ARM_PLL
|
|
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
|
|
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
select HAS_MCUX_CSI
|
|
select HAS_MCUX_EDMA
|
|
select HAS_MCUX_FLEXCAN
|
|
select HAS_MCUX_PWM
|
|
select HAS_MCUX_GPC
|
|
select HAS_MCUX_DCDC
|
|
select HAS_MCUX_PMU
|
|
select HAS_MCUX_IOMUXC
|
|
select HAS_MCUX_SRC
|
|
select HAS_SWO
|
|
|
|
config SOC_MIMXRT1061
|
|
bool "SOC_MIMXRT1061"
|
|
select SOC_SERIES_IMX_RT10XX
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_12B1MSPS_SAR
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_FLEXSPI
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_SEMC
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ARM_PLL
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
select HAS_MCUX_CSI
|
|
select HAS_MCUX_EDMA
|
|
select HAS_MCUX_FLEXCAN
|
|
select HAS_MCUX_GPC
|
|
select HAS_MCUX_DCDC
|
|
select HAS_MCUX_PMU
|
|
select HAS_MCUX_IOMUXC
|
|
select HAS_SWO
|
|
|
|
config SOC_MIMXRT1062
|
|
bool "SOC_MIMXRT1062"
|
|
select SOC_SERIES_IMX_RT10XX
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_12B1MSPS_SAR
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_ELCDIF
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_FLEXSPI
|
|
select HAS_MCUX_PWM
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_QTMR
|
|
select HAS_MCUX_SEMC
|
|
select HAS_MCUX_SNVS
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ARM_PLL
|
|
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
|
|
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
select HAS_MCUX_CSI
|
|
select HAS_MCUX_EDMA
|
|
select HAS_MCUX_FLEXCAN
|
|
select HAS_MCUX_I2S
|
|
select HAS_MCUX_GPC
|
|
select HAS_MCUX_DCDC
|
|
select HAS_MCUX_PMU
|
|
select HAS_MCUX_IOMUXC
|
|
select HAS_MCUX_ADC_ETC
|
|
select HAS_MCUX_SRC
|
|
select HAS_SWO
|
|
select HAS_MCUX_XBARA
|
|
|
|
config SOC_MIMXRT1064
|
|
bool "SOC_MIMXRT1064"
|
|
select SOC_SERIES_IMX_RT10XX
|
|
select HAS_MCUX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX_12B1MSPS_SAR
|
|
select HAS_MCUX_CCM
|
|
select HAS_MCUX_ELCDIF
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_FLEXSPI
|
|
select HAS_MCUX_PWM
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_QTMR
|
|
select HAS_MCUX_SEMC
|
|
select HAS_MCUX_SNVS
|
|
select HAS_MCUX_SRC
|
|
select HAS_MCUX_TRNG
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ARM_PLL
|
|
select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF
|
|
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
select HAS_MCUX_CSI
|
|
select HAS_MCUX_EDMA
|
|
select HAS_MCUX_FLEXCAN
|
|
select HAS_MCUX_GPC
|
|
select HAS_MCUX_DCDC
|
|
select HAS_MCUX_PMU
|
|
select HAS_MCUX_IOMUXC
|
|
select HAS_SWO
|
|
|
|
config SOC_MIMXRT1176_CM7
|
|
bool "SOC_MIMXRT1176_CM7"
|
|
select CPU_CORTEX_M7
|
|
select CPU_CORTEX_M_HAS_DWT
|
|
select SOC_SERIES_IMX_RT11XX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX
|
|
select HAS_MCUX_SEMC
|
|
select HAS_MCUX_CCM_REV2
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPADC
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_ELCDIF
|
|
select HAS_MCUX_MIPI_DSI
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_FLEXSPI
|
|
select HAS_MCUX_FLEXCAN
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ARM_PLL
|
|
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
|
|
select INIT_VIDEO_PLL
|
|
select HAS_MCUX_EDMA
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select ADJUST_DCDC
|
|
select BYPASS_LDO_LPSR
|
|
select ADJUST_LDO
|
|
select HAS_MCUX_PWM
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_GPC
|
|
select HAS_MCUX_I2S
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_ACMP
|
|
select HAS_MCUX_SRC_V2
|
|
select HAS_MCUX_IOMUXC
|
|
select HAS_SWO
|
|
|
|
config SOC_MIMXRT1176_CM4
|
|
bool "SOC_MIMXRT1176_CM4"
|
|
select CPU_CORTEX_M4
|
|
select SOC_SERIES_IMX_RT11XX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX
|
|
select HAS_MCUX_SEMC
|
|
select HAS_MCUX_CCM_REV2
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_FLEXSPI
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_GPT
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ARM_PLL
|
|
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
|
|
select INIT_VIDEO_PLL
|
|
select HAS_MCUX_EDMA
|
|
select HAS_MCUX_PWM
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_GPC
|
|
select HAS_MCUX_I2S
|
|
select HAS_MCUX_ACMP
|
|
select HAS_MCUX_SRC_V2
|
|
select HAS_MCUX_IOMUXC
|
|
select HAS_SWO
|
|
|
|
config SOC_MIMXRT1166_CM7
|
|
bool "SOC_MIMXRT1166_CM7"
|
|
select CPU_CORTEX_M7
|
|
select CPU_CORTEX_M_HAS_DWT
|
|
select SOC_SERIES_IMX_RT11XX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX
|
|
select HAS_MCUX_SEMC
|
|
select HAS_MCUX_CCM_REV2
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPADC
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_FLEXSPI
|
|
select HAS_MCUX_GPT
|
|
select HAS_MCUX_FLEXCAN
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ARM_PLL
|
|
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
|
|
select INIT_VIDEO_PLL
|
|
select HAS_MCUX_EDMA
|
|
select CPU_HAS_FPU_DOUBLE_PRECISION
|
|
select ADJUST_DCDC
|
|
select BYPASS_LDO_LPSR
|
|
select ADJUST_LDO
|
|
select HAS_MCUX_PWM
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_GPC
|
|
select HAS_MCUX_USB_EHCI
|
|
select HAS_MCUX_SRC_V2
|
|
select HAS_MCUX_IOMUXC
|
|
select HAS_SWO
|
|
|
|
|
|
config SOC_MIMXRT1166_CM4
|
|
bool "SOC_MIMXRT1166_CM4"
|
|
select CPU_CORTEX_M4
|
|
select SOC_SERIES_IMX_RT11XX
|
|
select HAS_MCUX_CACHE
|
|
select HAS_MCUX
|
|
select HAS_MCUX_SEMC
|
|
select HAS_MCUX_CCM_REV2
|
|
select HAS_MCUX_IGPIO
|
|
select HAS_MCUX_LPI2C
|
|
select HAS_MCUX_LPSPI
|
|
select HAS_MCUX_LPUART
|
|
select HAS_MCUX_FLEXSPI
|
|
select HAS_MCUX_GPT
|
|
select CPU_HAS_ARM_MPU
|
|
select INIT_ARM_PLL
|
|
select INIT_ENET_PLL if NET_L2_ETHERNET && ETH_DRIVER
|
|
select INIT_VIDEO_PLL
|
|
select HAS_MCUX_EDMA
|
|
select HAS_MCUX_PWM
|
|
select HAS_MCUX_USDHC1
|
|
select HAS_MCUX_USDHC2
|
|
select HAS_MCUX_ENET
|
|
select HAS_MCUX_GPC
|
|
select HAS_MCUX_SRC_V2
|
|
select HAS_MCUX_IOMUXC
|
|
select HAS_SWO
|
|
|
|
endchoice
|
|
|
|
if SOC_SERIES_IMX_RT
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1011CAE4A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1011DAE5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1015CAF4A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1015DAF5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1021CAF4A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1021CAG4A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1021DAF5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1021DAG5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1024CAG4A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1024DAG5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1051CVL5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1051DVL6A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1052CVJ5B
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1052CVL5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1052CVL5B
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1052DVJ6B
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1052DVL6A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1052DVL6B
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1061CVL5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1061DVL6A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1062CVJ5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1062CVJ5B
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1062CVL5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1062DVJ6A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1062DVL6A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1064CVL5A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1064DVL6A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1166DVM6A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1176AVM8A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1176CVM8A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1176DVMAA
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1175AVM8A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1175CVM8A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1175DVMAA
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1173CVM8A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1172AVM8A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1172CVM8A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1172DVMAA
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1171AVM8A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1171CVM8A
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_MIMXRT1171DVMAA
|
|
bool
|
|
|
|
config SOC_PART_NUMBER_IMX_RT
|
|
string
|
|
default "MIMXRT1011CAE4A" if SOC_PART_NUMBER_MIMXRT1011CAE4A
|
|
default "MIMXRT1011DAE5A" if SOC_PART_NUMBER_MIMXRT1011DAE5A
|
|
default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A
|
|
default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A
|
|
default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A
|
|
default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A
|
|
default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A
|
|
default "MIMXRT1021DAG5A" if SOC_PART_NUMBER_MIMXRT1021DAG5A
|
|
default "MIMXRT1024CAG4A" if SOC_PART_NUMBER_MIMXRT1024CAG4A
|
|
default "MIMXRT1024DAG5A" if SOC_PART_NUMBER_MIMXRT1024DAG5A
|
|
default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A
|
|
default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A
|
|
default "MIMXRT1052CVJ5B" if SOC_PART_NUMBER_MIMXRT1052CVJ5B
|
|
default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A
|
|
default "MIMXRT1052CVL5B" if SOC_PART_NUMBER_MIMXRT1052CVL5B
|
|
default "MIMXRT1052DVJ6B" if SOC_PART_NUMBER_MIMXRT1052DVJ6B
|
|
default "MIMXRT1052DVL6A" if SOC_PART_NUMBER_MIMXRT1052DVL6A
|
|
default "MIMXRT1052DVL6B" if SOC_PART_NUMBER_MIMXRT1052DVL6B
|
|
default "MIMXRT1061CVL5A" if SOC_PART_NUMBER_MIMXRT1061CVL5A
|
|
default "MIMXRT1061DVL6A" if SOC_PART_NUMBER_MIMXRT1061DVL6A
|
|
default "MIMXRT1062CVJ5A" if SOC_PART_NUMBER_MIMXRT1062CVJ5A
|
|
default "MIMXRT1062CVJ5B" if SOC_PART_NUMBER_MIMXRT1062CVJ5B
|
|
default "MIMXRT1062CVL5A" if SOC_PART_NUMBER_MIMXRT1062CVL5A
|
|
default "MIMXRT1062DVJ6A" if SOC_PART_NUMBER_MIMXRT1062DVJ6A
|
|
default "MIMXRT1062DVL6A" if SOC_PART_NUMBER_MIMXRT1062DVL6A
|
|
default "MIMXRT1064CVL5A" if SOC_PART_NUMBER_MIMXRT1064CVL5A
|
|
default "MIMXRT1064DVL6A" if SOC_PART_NUMBER_MIMXRT1064DVL6A
|
|
default "MIMXRT1176AVM8A" if SOC_PART_NUMBER_MIMXRT1176AVM8A
|
|
default "MIMXRT1176CVM8A" if SOC_PART_NUMBER_MIMXRT1176CVM8A
|
|
default "MIMXRT1176DVMAA" if SOC_PART_NUMBER_MIMXRT1176DVMAA
|
|
default "MIMXRT1166DVM6A" if SOC_PART_NUMBER_MIMXRT1166DVM6A
|
|
default "MIMXRT1175AVM8A" if SOC_PART_NUMBER_MIMXRT1175AVM8A
|
|
default "MIMXRT1175CVM8A" if SOC_PART_NUMBER_MIMXRT1175CVM8A
|
|
default "MIMXRT1175DVMAA" if SOC_PART_NUMBER_MIMXRT1175DVMAA
|
|
default "MIMXRT1173CVM8A" if SOC_PART_NUMBER_MIMXRT1173CVM8A
|
|
default "MIMXRT1172AVM8A" if SOC_PART_NUMBER_MIMXRT1172AVM8A
|
|
default "MIMXRT1172CVM8A" if SOC_PART_NUMBER_MIMXRT1172CVM8A
|
|
default "MIMXRT1172DVMAA" if SOC_PART_NUMBER_MIMXRT1172DVMAA
|
|
default "MIMXRT1171AVM8A" if SOC_PART_NUMBER_MIMXRT1171AVM8A
|
|
default "MIMXRT1171CVM8A" if SOC_PART_NUMBER_MIMXRT1171CVM8A
|
|
default "MIMXRT1171DVMAA" if SOC_PART_NUMBER_MIMXRT1171DVMAA
|
|
help
|
|
This string holds the full part number of the SoC. It is a hidden option
|
|
that you should not set directly. The part number selection choice defines
|
|
the default value for this string.
|
|
|
|
config SOC_SERIES_IMX_RT10XX
|
|
bool "i.MX RT 10XX Series"
|
|
select CPU_CORTEX_M7
|
|
select CPU_CORTEX_M_HAS_DWT
|
|
|
|
config SOC_SERIES_IMX_RT11XX
|
|
bool "i.MX RT 11XX Series"
|
|
|
|
config INIT_ARM_PLL
|
|
bool "Initialize ARM PLL"
|
|
|
|
config INIT_VIDEO_PLL
|
|
bool "Initialize Video PLL"
|
|
|
|
config INIT_ENET_PLL
|
|
bool
|
|
help
|
|
If y, the Ethernet PLL is initialized. Always enabled on e.g.
|
|
MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection
|
|
for MIMXRT1021").
|
|
|
|
config HAS_ARM_DIV
|
|
bool "Has the divider for ARM"
|
|
default y
|
|
|
|
config ARM_DIV
|
|
int "ARM clock divider"
|
|
range 0 7
|
|
default 0
|
|
|
|
config AHB_DIV
|
|
int "AHB clock divider"
|
|
range 0 7
|
|
default 0
|
|
|
|
config IPG_DIV
|
|
int "IPG clock divider"
|
|
range 0 3
|
|
default 0
|
|
|
|
config DCDC_VALUE
|
|
hex "DCDC value for VDD_SOC"
|
|
default 0x13
|
|
|
|
config ADJUST_DCDC
|
|
bool "Adjust internal DCDC output"
|
|
|
|
config BYPASS_LDO_LPSR
|
|
bool "Bypass LDO lpsr"
|
|
|
|
config ADJUST_LDO
|
|
bool "Adjust LDO setting"
|
|
|
|
config PM_MCUX_GPC
|
|
bool "MCUX general power controller driver"
|
|
|
|
config PM_MCUX_DCDC
|
|
bool "MCUX dcdc converter module driver"
|
|
|
|
config PM_MCUX_PMU
|
|
bool "MCUX power management unit driver"
|
|
|
|
menuconfig NXP_IMX_RT_BOOT_HEADER
|
|
bool "Boot header"
|
|
depends on !BOOTLOADER_MCUBOOT
|
|
help
|
|
Enable data structures required by the boot ROM to boot the
|
|
application from an external flash device.
|
|
|
|
if NXP_IMX_RT_BOOT_HEADER
|
|
|
|
choice BOOT_DEVICE
|
|
prompt "Boot device selection"
|
|
default BOOT_FLEXSPI_NOR
|
|
|
|
config BOOT_FLEXSPI_NOR
|
|
bool "FlexSPI serial NOR"
|
|
|
|
config BOOT_FLEXSPI_NAND
|
|
bool "FlexSPI serial NAND"
|
|
|
|
config BOOT_SEMC_NOR
|
|
bool "SEMC parallel NOR"
|
|
|
|
config BOOT_SEMC_NAND
|
|
bool "SEMC parallel NAND"
|
|
|
|
endchoice
|
|
|
|
config FLEXSPI_CONFIG_BLOCK_OFFSET
|
|
hex "FlexSPI config block offset"
|
|
default 0x0 if BOOT_FLEXSPI_NOR
|
|
help
|
|
FlexSPI configuration block consists of parameters regarding specific
|
|
flash devices including read command sequence, quad mode enablement
|
|
sequence (optional), etc. The boot ROM expects FlexSPI configuration
|
|
parameter to be presented in serial nor flash.
|
|
|
|
config IMAGE_VECTOR_TABLE_OFFSET
|
|
hex "Image vector table offset"
|
|
default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
|
|
default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND
|
|
help
|
|
The Image Vector Table (IVT) provides the boot ROM with pointers to
|
|
the application entry point and device configuration data. The boot
|
|
ROM requires a fixed IVT offset for each type of boot device.
|
|
|
|
config DEVICE_CONFIGURATION_DATA
|
|
bool "Device configuration data"
|
|
default y if HAS_MCUX_SEMC
|
|
help
|
|
Device configuration data (DCD) provides a sequence of commands to
|
|
the boot ROM to initialize components such as an SDRAM.
|
|
|
|
endif # NXP_IMX_RT_BOOT_HEADER
|
|
|
|
choice CODE_LOCATION
|
|
prompt "Code location selection"
|
|
default CODE_ITCM
|
|
|
|
config CODE_SEMC
|
|
bool "Link code into external SEMC-controlled memory"
|
|
|
|
config CODE_ITCM
|
|
bool "Link code into internal instruction tightly coupled memory (ITCM)"
|
|
|
|
config CODE_FLEXSPI
|
|
bool "Link code into external FlexSPI-controlled memory"
|
|
imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT
|
|
|
|
config CODE_FLEXSPI2
|
|
bool "Link code into internal FlexSPI-controlled memory"
|
|
imply NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT
|
|
|
|
config CODE_SRAM0
|
|
bool "Link code into RAM_L memory (RAM_L)"
|
|
endchoice
|
|
|
|
config OCRAM_NOCACHE
|
|
bool "Create noncacheable OCRAM region"
|
|
select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
|
|
select PLATFORM_SPECIFIC_INIT
|
|
help
|
|
Creates linker section and MPU region for OCRAM region with
|
|
noncacheable attribute. OCRAM memory is useful for fast DMA transfers.
|
|
|
|
|
|
endif # SOC_SERIES_IMX_RT
|