162 lines
5.4 KiB
C
162 lines
5.4 KiB
C
/*
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* Copyright (c) 2020 Linaro Ltd.
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* Copyright (c) 2020-2021 ATL Electronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief Cypress PSoC-6 MCU family devicetree helper macros
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*/
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#ifndef _CYPRESS_PSOC6_DT_H_
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#define _CYPRESS_PSOC6_DT_H_
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#include <zephyr/devicetree.h>
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/*
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* Devicetree macros related to interrupt
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*
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* The main "API" macro is CY_PSOC6_IRQ_CONFIG. It is an internal definition
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* used to configure the PSoC-6 interrupts in a generic way. This is necessary
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* because Cortex-M0+ can handle a limited number of interrupts and have
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* multiplexers in front of any NVIC interrupt line.
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*
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* The CY_PSOC6_IRQ_CONFIG expands from CY_PSOC6_DT_INST_NVIC_INSTALL, the
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* public API used by drivers. See below code fragment:
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*
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* static void <driver>_psoc6_isr(const struct device *dev)
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* {
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* ...
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* }
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*
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* #define <DRIVER>_PSOC6_INIT(n) \
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* ... \
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* static void <driver>_psoc6_irq_config(const struct device *port) \
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* { \
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* CY_PSOC6_DT_INST_NVIC_INSTALL(n, \
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* <driver>_psoc6_isr); \
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* }; \
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* };
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*
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* where:
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* n - driver instance number
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* isr - isr function to be called
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*
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* Cortex-M4 simple pass the parameter and constructs an usual NVIC
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* configuration code.
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*
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* The Cortex-M0+ must get from interrupt parent the interrupt line and
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* configure the interrupt channel to connect PSoC-6 peripheral interrupt to
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* Cortex-M0+ NVIC. The multiplexer is configured by CY_PSOC6_DT_NVIC_MUX_MAP
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* using the interrupt value from the interrupt parent.
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*
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* see cypress,psoc6-int-mux.yaml for devicetree documentation.
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*/
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#ifdef CONFIG_CPU_CORTEX_M0PLUS
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/* Cortex-M0+
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* - install config only when exists an interrupt_parent property
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* - get peripheral irq using PROP_BY_INDEX, to avoid translation from
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* interrupt-parent node property.
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* - configure interrupt channel using the channel number register value from
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* interrupt-parent node.
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*/
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#define CY_PSOC6_DT_INST_NVIC_INSTALL(n, isr) \
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IF_ENABLED(DT_INST_NODE_HAS_PROP(n, interrupt_parent),\
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(CY_PSOC6_IRQ_CONFIG(n, isr)))
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#define CY_PSOC6_NVIC_MUX_IRQN(n) DT_IRQN(DT_INST_PHANDLE_BY_IDX(n,\
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interrupt_parent, 0))
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#define CY_PSOC6_NVIC_MUX_IRQ_PRIO(n) DT_IRQ(DT_INST_PHANDLE_BY_IDX(n,\
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interrupt_parent, 0), priority)
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/*
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* DT_INST_PROP_BY_IDX should be used get interrupt and configure, instead
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* DT_INST_IRQN. The DT_INST_IRQN return IRQ number with level translation,
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* since it uses interrupt-parent, and the value at Cortex-M0 NVIC multiplexers
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* will be wrong.
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*
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* See multi-level-interrupt-handling.
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*/
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#define CY_PSOC6_NVIC_MUX_MAP(n) Cy_SysInt_SetInterruptSource( \
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DT_IRQN(DT_INST_PHANDLE_BY_IDX(n,\
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interrupt_parent, 0)), \
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DT_INST_PROP_BY_IDX(n, interrupts, 0))
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#else
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/* Cortex-M4
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* - bypass config
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* - uses irq directly from peripheral devicetree definition
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* - no map/translations
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*/
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#define CY_PSOC6_DT_INST_NVIC_INSTALL(n, isr) CY_PSOC6_IRQ_CONFIG(n, isr)
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#define CY_PSOC6_NVIC_MUX_IRQN(n) DT_INST_IRQN(n)
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#define CY_PSOC6_NVIC_MUX_IRQ_PRIO(n) DT_INST_IRQ(n, priority)
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#define CY_PSOC6_NVIC_MUX_MAP(n)
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#endif
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#define CY_PSOC6_IRQ_CONFIG(n, isr) \
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do { \
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IRQ_CONNECT(CY_PSOC6_NVIC_MUX_IRQN(n), \
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CY_PSOC6_NVIC_MUX_IRQ_PRIO(n),\
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isr, DEVICE_DT_INST_GET(n), 0);\
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CY_PSOC6_NVIC_MUX_MAP(n); \
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irq_enable(CY_PSOC6_NVIC_MUX_IRQN(n)); \
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} while (false)
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/*
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* Devicetree related macros to construct pin control config data
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*/
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/* Get GPIO register address associated with pinctrl-0 pin at index 'i' */
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#define CY_PSOC6_PIN_TO_GPIO_REG_ADDR(inst, i) \
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DT_REG_ADDR(DT_PHANDLE(DT_INST_PINCTRL_0(inst, i), cypress_pins))
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/* Get PIN associated with pinctrl-0 pin at index 'i' */
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#define CY_PSOC6_PIN(inst, i) \
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DT_PHA(DT_INST_PINCTRL_0(inst, i), cypress_pins, pin)
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/* Get HSIOM value associated with pinctrl-0 pin at index 'i' */
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#define CY_PSOC6_PIN_HSIOM(inst, i) \
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DT_PHA(DT_INST_PINCTRL_0(inst, i), cypress_pins, hsiom)
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/* Helper function for CY_PSOC6_PIN_FLAGS */
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#define CY_PSOC6_PIN_FLAG(inst, i, flag) \
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DT_PROP(DT_INST_PINCTRL_0(inst, i), flag)
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/* Convert DT flags to SoC flags */
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#define CY_PSOC6_PIN_FLAGS(inst, i) \
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(CY_PSOC6_PIN_FLAG(inst, i, bias_pull_up) << \
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SOC_GPIO_PULLUP_POS | \
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CY_PSOC6_PIN_FLAG(inst, i, bias_pull_down) << \
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SOC_GPIO_PULLUP_POS | \
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CY_PSOC6_PIN_FLAG(inst, i, drive_open_drain) << \
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SOC_GPIO_OPENDRAIN_POS | \
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CY_PSOC6_PIN_FLAG(inst, i, drive_open_source) << \
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SOC_GPIO_OPENSOURCE_POS | \
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CY_PSOC6_PIN_FLAG(inst, i, drive_push_pull) << \
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SOC_GPIO_PUSHPULL_POS | \
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CY_PSOC6_PIN_FLAG(inst, i, input_enable) << \
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SOC_GPIO_INPUTENABLE_POS)
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/* Construct a soc_pio_pin element for pin cfg */
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#define CY_PSOC6_DT_INST_PIN(inst, idx) \
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{ \
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(GPIO_PRT_Type *)CY_PSOC6_PIN_TO_GPIO_REG_ADDR(inst, idx), \
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CY_PSOC6_PIN(inst, idx), \
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CY_PSOC6_PIN_HSIOM(inst, idx) << SOC_GPIO_FUNC_POS | \
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CY_PSOC6_PIN_FLAGS(inst, idx) \
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}
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/* Get the number of pins for pinctrl-0 */
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#define CY_PSOC6_DT_INST_NUM_PINS(inst) DT_INST_NUM_PINCTRLS_BY_IDX(inst, 0)
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/* internal macro to structure things for use with UTIL_LISTIFY */
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#define CY_PSOC6_PIN_ELEM(idx, inst) CY_PSOC6_DT_INST_PIN(inst, idx)
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/* Construct an array initializer for soc_gpio_pin for a device instance */
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#define CY_PSOC6_DT_INST_PINS(inst) \
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{ LISTIFY(CY_PSOC6_DT_INST_NUM_PINS(inst), \
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CY_PSOC6_PIN_ELEM, (,), inst) \
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}
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#endif /* _CYPRESS_PSOC6_SOC_DT_H_ */
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