zephyr/arch/riscv
Mateusz Sierszulski 2ed5763baa arch: riscv: core: Place vectors section through zephyr_linker_sources()
This commit is fixing placing the vectors section through
zephyr_linker_sources(ROM_START ...) (as done in the ARM
architecture port) so its order can be adjusted by SORT_KEY.

Fixes #49903

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
2022-09-08 10:39:31 +02:00
..
core arch: riscv: core: Place vectors section through zephyr_linker_sources() 2022-09-08 10:39:31 +02:00
include riscv: Introduce RISCV_ALWAYS_SWITCH_THROUGH_ECALL 2022-07-04 18:18:10 +02:00
CMakeLists.txt
Kconfig riscv: Use IRQ vector table for vectored mode 2022-07-07 10:00:20 +02:00
Kconfig.core riscv: Introduce Zicsr and Zifencei extensions 2022-08-29 16:57:18 +02:00
Kconfig.isa riscv: Introduce BitManip extensions 2022-08-29 16:57:18 +02:00