122 lines
2.2 KiB
Plaintext
122 lines
2.2 KiB
Plaintext
/*
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* Copyright (c) 2022 Nordic Semiconductor
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* SPDX-License-Identifier: Apache-2.0
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*/
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&pinctrl {
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uart0_default: uart0_default {
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group1 {
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psels = <NRF_PSEL(UART_TX, 0, 6)>,
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<NRF_PSEL(UART_RX, 0, 8)>,
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<NRF_PSEL(UART_RTS, 0, 5)>,
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<NRF_PSEL(UART_CTS, 0, 7)>;
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};
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};
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uart0_sleep: uart0_sleep {
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group1 {
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psels = <NRF_PSEL(UART_TX, 0, 6)>,
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<NRF_PSEL(UART_RX, 0, 8)>,
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<NRF_PSEL(UART_RTS, 0, 5)>,
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<NRF_PSEL(UART_CTS, 0, 7)>;
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low-power-enable;
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};
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};
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i2c0_default: i2c0_default {
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group1 {
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psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
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<NRF_PSEL(TWIM_SCL, 0, 27)>;
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};
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};
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i2c0_sleep: i2c0_sleep {
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group1 {
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psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
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<NRF_PSEL(TWIM_SCL, 0, 27)>;
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low-power-enable;
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};
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};
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i2c1_default: i2c1_default {
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group1 {
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psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
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<NRF_PSEL(TWIM_SCL, 0, 31)>;
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};
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};
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i2c1_sleep: i2c1_sleep {
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group1 {
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psels = <NRF_PSEL(TWIM_SDA, 0, 30)>,
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<NRF_PSEL(TWIM_SCL, 0, 31)>;
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low-power-enable;
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};
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};
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pwm0_default: pwm0_default {
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group1 {
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psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
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nordic,invert;
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};
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};
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pwm0_sleep: pwm0_sleep {
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group1 {
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psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
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low-power-enable;
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};
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};
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spi0_default: spi0_default {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 0, 27)>,
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<NRF_PSEL(SPIM_MOSI, 0, 26)>,
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<NRF_PSEL(SPIM_MISO, 0, 28)>;
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};
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};
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spi0_sleep: spi0_sleep {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 0, 27)>,
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<NRF_PSEL(SPIM_MOSI, 0, 26)>,
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<NRF_PSEL(SPIM_MISO, 0, 28)>;
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low-power-enable;
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};
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};
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spi1_default: spi1_default {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
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<NRF_PSEL(SPIM_MOSI, 0, 30)>,
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<NRF_PSEL(SPIM_MISO, 0, 29)>;
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};
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};
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spi1_sleep: spi1_sleep {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 0, 31)>,
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<NRF_PSEL(SPIM_MOSI, 0, 30)>,
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<NRF_PSEL(SPIM_MISO, 0, 29)>;
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low-power-enable;
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};
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};
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spi2_default: spi2_default {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 0, 25)>,
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<NRF_PSEL(SPIM_MOSI, 0, 23)>,
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<NRF_PSEL(SPIM_MISO, 0, 24)>;
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};
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};
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spi2_sleep: spi2_sleep {
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group1 {
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psels = <NRF_PSEL(SPIM_SCK, 0, 25)>,
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<NRF_PSEL(SPIM_MOSI, 0, 23)>,
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<NRF_PSEL(SPIM_MISO, 0, 24)>;
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low-power-enable;
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};
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};
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};
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