393 lines
11 KiB
C
393 lines
11 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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* Copyright (c) 2016 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief Driver for UART port on STM32F10x family processor.
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*
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* Based on reference manual:
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* STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx
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* advanced ARM ® -based 32-bit MCUs
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*
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* Chapter 27: Universal synchronous asynchronous receiver
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* transmitter (USART)
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <misc/__assert.h>
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#include <board.h>
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#include <init.h>
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#include <uart.h>
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#include <clock_control.h>
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#include <sections.h>
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#include <clock_control/stm32_clock_control.h>
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#include "uart_stm32.h"
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/* convenience defines */
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#define DEV_CFG(dev) \
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((const struct uart_stm32_config * const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct uart_stm32_data * const)(dev)->driver_data)
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#define UART_STRUCT(dev) \
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((USART_TypeDef *)(DEV_CFG(dev))->uconf.base)
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#define TIMEOUT 1000
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static int uart_stm32_poll_in(struct device *dev, unsigned char *c)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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if (HAL_UART_Receive(UartHandle, (u8_t *)c, 1, TIMEOUT) == HAL_OK) {
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return 0;
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} else {
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return -1;
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}
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}
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static unsigned char uart_stm32_poll_out(struct device *dev,
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unsigned char c)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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HAL_UART_Transmit(UartHandle, (u8_t *)&c, 1, TIMEOUT);
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return c;
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}
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static inline void __uart_stm32_get_clock(struct device *dev)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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struct device *clk =
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device_get_binding(STM32_CLOCK_CONTROL_NAME);
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__ASSERT_NO_MSG(clk);
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data->clock = clk;
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}
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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static int uart_stm32_fifo_fill(struct device *dev, const u8_t *tx_data,
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int size)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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u8_t num_tx = 0;
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while ((size - num_tx > 0) && __HAL_UART_GET_FLAG(UartHandle,
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UART_FLAG_TXE)) {
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/* TXE flag will be cleared with byte write to DR register */
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/* Send a character (8bit , parity none) */
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#if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32F4X)
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/* Use direct access for F1, F4 until Low Level API is available
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* Once it is we can remove the if/else
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*/
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UartHandle->Instance->DR = (tx_data[num_tx++] &
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(u8_t)0x00FF);
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#else
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LL_USART_TransmitData8(UartHandle->Instance, tx_data[num_tx++]);
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#endif
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}
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return num_tx;
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}
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static int uart_stm32_fifo_read(struct device *dev, u8_t *rx_data,
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const int size)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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u8_t num_rx = 0;
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while ((size - num_rx > 0) && __HAL_UART_GET_FLAG(UartHandle,
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UART_FLAG_RXNE)) {
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/* Clear the interrupt */
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__HAL_UART_CLEAR_FLAG(UartHandle, UART_FLAG_RXNE);
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/* Receive a character (8bit , parity none) */
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#if defined(CONFIG_SOC_SERIES_STM32F1X) || defined(CONFIG_SOC_SERIES_STM32F4X)
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/* Use direct access for F1, F4 until Low Level API is available
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* Once it is we can remove the if/else
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*/
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rx_data[num_rx++] = (u8_t)(UartHandle->Instance->DR &
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(u8_t)0x00FF);
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#else
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rx_data[num_rx++] = LL_USART_ReceiveData8(UartHandle->Instance);
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#endif
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}
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return num_rx;
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}
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static void uart_stm32_irq_tx_enable(struct device *dev)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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__HAL_UART_ENABLE_IT(UartHandle, UART_IT_TC);
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}
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static void uart_stm32_irq_tx_disable(struct device *dev)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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__HAL_UART_DISABLE_IT(UartHandle, UART_IT_TC);
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}
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static int uart_stm32_irq_tx_ready(struct device *dev)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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return __HAL_UART_GET_FLAG(UartHandle, UART_FLAG_TXE);
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}
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static int uart_stm32_irq_tx_complete(struct device *dev)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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return __HAL_UART_GET_FLAG(UartHandle, UART_FLAG_TXE);
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}
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static void uart_stm32_irq_rx_enable(struct device *dev)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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__HAL_UART_ENABLE_IT(UartHandle, UART_IT_RXNE);
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}
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static void uart_stm32_irq_rx_disable(struct device *dev)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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__HAL_UART_DISABLE_IT(UartHandle, UART_IT_RXNE);
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}
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static int uart_stm32_irq_rx_ready(struct device *dev)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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return __HAL_UART_GET_FLAG(UartHandle, UART_FLAG_RXNE);
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}
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static void uart_stm32_irq_err_enable(struct device *dev)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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/* Enable FE, ORE interruptions */
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__HAL_UART_ENABLE_IT(UartHandle, UART_IT_ERR);
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/* Enable Line break detection */
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__HAL_UART_ENABLE_IT(UartHandle, UART_IT_LBD);
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/* Enable parity error interruption */
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__HAL_UART_ENABLE_IT(UartHandle, UART_IT_PE);
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}
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static void uart_stm32_irq_err_disable(struct device *dev)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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/* Disable FE, ORE interruptions */
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__HAL_UART_DISABLE_IT(UartHandle, UART_IT_ERR);
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/* Disable Line break detection */
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__HAL_UART_DISABLE_IT(UartHandle, UART_IT_LBD);
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/* Disable parity error interruption */
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__HAL_UART_DISABLE_IT(UartHandle, UART_IT_PE);
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}
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static int uart_stm32_irq_is_pending(struct device *dev)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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return __HAL_UART_GET_FLAG(UartHandle, UART_FLAG_TXE | UART_FLAG_RXNE);
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}
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static int uart_stm32_irq_update(struct device *dev)
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{
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return 1;
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}
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static void uart_stm32_irq_callback_set(struct device *dev,
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uart_irq_callback_t cb)
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{
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struct uart_stm32_data *data = DEV_DATA(dev);
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data->user_cb = cb;
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}
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static void uart_stm32_isr(void *arg)
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{
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struct device *dev = arg;
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struct uart_stm32_data *data = DEV_DATA(dev);
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if (data->user_cb) {
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data->user_cb(dev);
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}
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}
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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static const struct uart_driver_api uart_stm32_driver_api = {
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.poll_in = uart_stm32_poll_in,
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.poll_out = uart_stm32_poll_out,
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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.fifo_fill = uart_stm32_fifo_fill,
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.fifo_read = uart_stm32_fifo_read,
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.irq_tx_enable = uart_stm32_irq_tx_enable,
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.irq_tx_disable = uart_stm32_irq_tx_disable,
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.irq_tx_ready = uart_stm32_irq_tx_ready,
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.irq_tx_complete = uart_stm32_irq_tx_complete,
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.irq_rx_enable = uart_stm32_irq_rx_enable,
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.irq_rx_disable = uart_stm32_irq_rx_disable,
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.irq_rx_ready = uart_stm32_irq_rx_ready,
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.irq_err_enable = uart_stm32_irq_err_enable,
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.irq_err_disable = uart_stm32_irq_err_disable,
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.irq_is_pending = uart_stm32_irq_is_pending,
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.irq_update = uart_stm32_irq_update,
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.irq_callback_set = uart_stm32_irq_callback_set,
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#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
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};
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/**
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* @brief Initialize UART channel
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*
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* This routine is called to reset the chip in a quiescent state.
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* It is assumed that this function is called only once per UART.
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*
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* @param dev UART device struct
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*
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* @return 0
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*/
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static int uart_stm32_init(struct device *dev)
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{
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const struct uart_stm32_config *config = DEV_CFG(dev);
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struct uart_stm32_data *data = DEV_DATA(dev);
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UART_HandleTypeDef *UartHandle = &data->huart;
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__uart_stm32_get_clock(dev);
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/* enable clock */
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clock_control_on(data->clock,
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(clock_control_subsys_t *)&config->pclken);
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UartHandle->Instance = UART_STRUCT(dev);
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UartHandle->Init.WordLength = UART_WORDLENGTH_8B;
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UartHandle->Init.StopBits = UART_STOPBITS_1;
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UartHandle->Init.Parity = UART_PARITY_NONE;
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UartHandle->Init.HwFlowCtl = UART_HWCONTROL_NONE;
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UartHandle->Init.Mode = UART_MODE_TX_RX;
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UartHandle->Init.OverSampling = UART_OVERSAMPLING_16;
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HAL_UART_Init(UartHandle);
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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config->uconf.irq_config_func(dev);
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#endif
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return 0;
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}
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/* Define clocks */
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#define STM32_CLOCK_UART(type, apb, n) \
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.pclken = { .bus = STM32_CLOCK_BUS_ ## apb, \
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.enr = LL_##apb##_GRP1_PERIPH_##type##n }
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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#define STM32_UART_IRQ_HANDLER_DECL(n) \
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static void uart_stm32_irq_config_func_##n(struct device *dev)
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#define STM32_UART_IRQ_HANDLER_FUNC(n) \
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.irq_config_func = uart_stm32_irq_config_func_##n,
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#define STM32_UART_IRQ_HANDLER(n) \
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static void uart_stm32_irq_config_func_##n(struct device *dev) \
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{ \
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IRQ_CONNECT(PORT_ ## n ## _IRQ, \
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CONFIG_UART_STM32_PORT_ ## n ## _IRQ_PRI, \
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uart_stm32_isr, DEVICE_GET(uart_stm32_ ## n), \
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0); \
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irq_enable(PORT_ ## n ## _IRQ); \
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}
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#else
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#define STM32_UART_IRQ_HANDLER_DECL(n)
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#define STM32_UART_IRQ_HANDLER_FUNC(n)
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#define STM32_UART_IRQ_HANDLER(n)
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#endif
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#define UART_DEVICE_INIT_STM32(type, n, apb) \
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STM32_UART_IRQ_HANDLER_DECL(n); \
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\
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static const struct uart_stm32_config uart_stm32_dev_cfg_##n = { \
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.uconf = { \
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.base = (u8_t *)CONFIG_UART_STM32_PORT_ ## n ## _BASE_ADDRESS, \
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STM32_UART_IRQ_HANDLER_FUNC(n) \
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}, \
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STM32_CLOCK_UART(type, apb, n), \
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}; \
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\
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static struct uart_stm32_data uart_stm32_dev_data_##n = { \
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.huart = { \
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.Init = { \
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.BaudRate = CONFIG_UART_STM32_PORT_##n##_BAUD_RATE \
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} \
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} \
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}; \
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\
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DEVICE_AND_API_INIT(uart_stm32_##n, CONFIG_UART_STM32_PORT_##n##_NAME, \
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&uart_stm32_init, \
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&uart_stm32_dev_data_##n, &uart_stm32_dev_cfg_##n, \
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PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&uart_stm32_driver_api); \
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\
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STM32_UART_IRQ_HANDLER(n)
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#ifdef CONFIG_UART_STM32_PORT_1
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UART_DEVICE_INIT_STM32(USART, 1, APB2)
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#endif /* CONFIG_UART_STM32_PORT_1 */
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#ifdef CONFIG_UART_STM32_PORT_2
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UART_DEVICE_INIT_STM32(USART, 2, APB1)
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#endif /* CONFIG_UART_STM32_PORT_2 */
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#ifdef CONFIG_UART_STM32_PORT_3
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UART_DEVICE_INIT_STM32(USART, 3, APB1)
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#endif /* CONFIG_UART_STM32_PORT_3 */
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#ifdef CONFIG_UART_STM32_PORT_4
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UART_DEVICE_INIT_STM32(UART, 4, APB1)
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#endif /* CONFIG_UART_STM32_PORT_4 */
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#ifdef CONFIG_UART_STM32_PORT_5
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UART_DEVICE_INIT_STM32(UART, 5, APB1)
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#endif /* CONFIG_UART_STM32_PORT_5 */
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#ifdef CONFIG_UART_STM32_PORT_6
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UART_DEVICE_INIT_STM32(USART, 6, APB2)
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#endif /* CONFIG_UART_STM32_PORT_6 */
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#ifdef CONFIG_UART_STM32_PORT_7
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UART_DEVICE_INIT_STM32(UART, 7, APB1)
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#endif /* CONFIG_UART_STM32_PORT_7 */
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#ifdef CONFIG_UART_STM32_PORT_8
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UART_DEVICE_INIT_STM32(UART, 8, APB1)
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#endif /* CONFIG_UART_STM32_PORT_8 */
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#ifdef CONFIG_UART_STM32_PORT_9
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UART_DEVICE_INIT_STM32(UART, 9, APB2)
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#endif /* CONFIG_UART_STM32_PORT_9 */
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#ifdef CONFIG_UART_STM32_PORT_10
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UART_DEVICE_INIT_STM32(UART, 10, APB2)
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#endif /* CONFIG_UART_STM32_PORT_10 */
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