297 lines
7.9 KiB
C
297 lines
7.9 KiB
C
/*
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*
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* Copyright (c) 2019 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <clock_control.h>
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#include <sys/util.h>
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#include <clock_control/stm32_clock_control.h>
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/* Macros to fill up prescaler values */
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#define z_sysclk_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
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#define sysclk_prescaler(v) z_sysclk_prescaler(v)
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#define z_ahb_prescaler(v) LL_RCC_AHB_DIV_ ## v
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#define ahb_prescaler(v) z_ahb_prescaler(v)
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#define z_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
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#define apb1_prescaler(v) z_apb1_prescaler(v)
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#define z_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v
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#define apb2_prescaler(v) z_apb2_prescaler(v)
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#define z_apb3_prescaler(v) LL_RCC_APB3_DIV_ ## v
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#define apb3_prescaler(v) z_apb3_prescaler(v)
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#define z_apb4_prescaler(v) LL_RCC_APB4_DIV_ ## v
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#define apb4_prescaler(v) z_apb4_prescaler(v)
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#if defined(CONFIG_CPU_CORTEX_M7)
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#if CONFIG_CLOCK_STM32_D1CPRE > 1
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/*
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* D1CPRE prescaler allows to set a HCLK frequency lower than SYSCLK frequency.
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* Though, zephyr doesn't make a difference today between these two clocks.
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* So, changing this prescaler is not allowed until it is made possible to
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* use them independently in zephyr clock subsystem.
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*/
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#error "D1CPRE presacler can't be higher than 1"
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#endif
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#endif /* CONFIG_CPU_CORTEX_M7 */
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/**
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* @brief fill in AHB/APB buses configuration structure
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*/
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#if !defined(CONFIG_CPU_CORTEX_M4)
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static void config_bus_prescalers(void)
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{
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LL_RCC_SetSysPrescaler(sysclk_prescaler(CONFIG_CLOCK_STM32_D1CPRE));
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LL_RCC_SetAHBPrescaler(ahb_prescaler(CONFIG_CLOCK_STM32_HPRE));
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LL_RCC_SetAPB1Prescaler(apb1_prescaler(CONFIG_CLOCK_STM32_D2PPRE1));
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LL_RCC_SetAPB2Prescaler(apb2_prescaler(CONFIG_CLOCK_STM32_D2PPRE2));
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LL_RCC_SetAPB3Prescaler(apb3_prescaler(CONFIG_CLOCK_STM32_D1PPRE));
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LL_RCC_SetAPB4Prescaler(apb4_prescaler(CONFIG_CLOCK_STM32_D3PPRE));
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}
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#endif /* CONFIG_CPU_CORTEX_M4 */
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static u32_t get_bus_clock(u32_t clock, u32_t prescaler)
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{
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return clock / prescaler;
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}
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static inline int stm32_clock_control_on(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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ARG_UNUSED(dev);
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/* Both cores can access bansk by following LL API */
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/* Using "_Cn_" LL API would restrict access to one or the other */
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switch (pclken->bus) {
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case STM32_CLOCK_BUS_AHB1:
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LL_AHB1_GRP1_EnableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_AHB2:
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LL_AHB2_GRP1_EnableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_AHB3:
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LL_AHB3_GRP1_EnableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_AHB4:
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LL_AHB4_GRP1_EnableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB1:
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LL_APB1_GRP1_EnableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB1_2:
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LL_APB1_GRP2_EnableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB2:
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LL_APB2_GRP1_EnableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB3:
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LL_APB3_GRP1_EnableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB4:
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LL_APB4_GRP1_EnableClock(pclken->enr);
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static inline int stm32_clock_control_off(struct device *dev,
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clock_control_subsys_t sub_system)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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ARG_UNUSED(dev);
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/* Both cores can access bansk by following LL API */
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/* Using "_Cn_" LL API would restrict access to one or the other */
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switch (pclken->bus) {
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case STM32_CLOCK_BUS_AHB1:
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LL_AHB1_GRP1_DisableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_AHB2:
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LL_AHB2_GRP1_DisableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_AHB3:
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LL_AHB3_GRP1_DisableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_AHB4:
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LL_AHB4_GRP1_DisableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB1:
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LL_APB1_GRP1_DisableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB1_2:
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LL_APB1_GRP2_DisableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB2:
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LL_APB2_GRP1_DisableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB3:
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LL_APB3_GRP1_DisableClock(pclken->enr);
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break;
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case STM32_CLOCK_BUS_APB4:
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LL_APB4_GRP1_DisableClock(pclken->enr);
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static int stm32_clock_control_get_subsys_rate(struct device *clock,
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clock_control_subsys_t sub_system,
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u32_t *rate)
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{
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struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
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/*
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* Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
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* SystemCoreClock is preferred to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
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* since it will be updated after clock configuration and hence
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* more likely to contain actual clock speed
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*/
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u32_t sys_d1cpre_ck = get_bus_clock(SystemCoreClock,
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CONFIG_CLOCK_STM32_D1CPRE);
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u32_t ahb_clock = get_bus_clock(sys_d1cpre_ck,
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CONFIG_CLOCK_STM32_HPRE);
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u32_t apb1_clock = get_bus_clock(ahb_clock,
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CONFIG_CLOCK_STM32_D2PPRE1);
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u32_t apb2_clock = get_bus_clock(ahb_clock,
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CONFIG_CLOCK_STM32_D2PPRE2);
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u32_t apb3_clock = get_bus_clock(ahb_clock,
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CONFIG_CLOCK_STM32_D1PPRE);
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u32_t apb4_clock = get_bus_clock(ahb_clock,
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CONFIG_CLOCK_STM32_D3PPRE);
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ARG_UNUSED(clock);
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switch (pclken->bus) {
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case STM32_CLOCK_BUS_AHB1:
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case STM32_CLOCK_BUS_AHB2:
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case STM32_CLOCK_BUS_AHB3:
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case STM32_CLOCK_BUS_AHB4:
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*rate = ahb_clock;
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break;
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case STM32_CLOCK_BUS_APB1:
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case STM32_CLOCK_BUS_APB1_2:
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*rate = apb1_clock;
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break;
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case STM32_CLOCK_BUS_APB2:
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*rate = apb2_clock;
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break;
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case STM32_CLOCK_BUS_APB3:
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*rate = apb3_clock;
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break;
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case STM32_CLOCK_BUS_APB4:
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*rate = apb4_clock;
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break;
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default:
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return -ENOTSUP;
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}
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return 0;
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}
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static struct clock_control_driver_api stm32_clock_control_api = {
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.on = stm32_clock_control_on,
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.off = stm32_clock_control_off,
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.get_rate = stm32_clock_control_get_subsys_rate,
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};
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static int stm32_clock_control_init(struct device *dev)
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{
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ARG_UNUSED(dev);
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#if !defined(CONFIG_CPU_CORTEX_M4)
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#ifdef CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL
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/* Power Configuration */
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LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
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LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
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while (LL_PWR_IsActiveFlag_VOS() == 0) {
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}
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#ifdef CONFIG_CLOCK_STM32_PLL_SRC_HSE
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#ifdef CONFIG_CLOCK_STM32_HSE_BYPASS
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LL_RCC_HSE_EnableBypass();
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#else
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LL_RCC_HSE_DisableBypass();
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#endif /* CONFIG_CLOCK_STM32_HSE_BYPASS */
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/* Enable HSE oscillator */
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LL_RCC_HSE_Enable();
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while (LL_RCC_HSE_IsReady() != 1) {
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}
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/* Set FLASH latency */
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LL_FLASH_SetLatency(LL_FLASH_LATENCY_4);
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/* Main PLL configuration and activation */
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LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
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#else
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#error "CONFIG_CLOCK_STM32_PLL_SRC_HSE not selected"
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#endif /* CONFIG_CLOCK_STM32_PLL_SRC_HSE */
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/* Configure PLL1 */
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LL_RCC_PLL1P_Enable();
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LL_RCC_PLL1Q_Enable();
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LL_RCC_PLL1R_Enable();
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LL_RCC_PLL1FRACN_Disable();
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LL_RCC_PLL1_SetVCOInputRange(LL_RCC_PLLINPUTRANGE_2_4);
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LL_RCC_PLL1_SetVCOOutputRange(LL_RCC_PLLVCORANGE_WIDE);
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LL_RCC_PLL1_SetM(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
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LL_RCC_PLL1_SetN(CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER);
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LL_RCC_PLL1_SetP(CONFIG_CLOCK_STM32_PLL_P_DIVISOR);
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LL_RCC_PLL1_SetQ(CONFIG_CLOCK_STM32_PLL_Q_DIVISOR);
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LL_RCC_PLL1_SetR(CONFIG_CLOCK_STM32_PLL_R_DIVISOR);
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LL_RCC_PLL1_Enable();
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while (LL_RCC_PLL1_IsReady() != 1) {
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}
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/* Set buses (Sys,AHB, APB1, APB2 & APB4) prescalers */
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config_bus_prescalers();
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/* Set PLL1 as System Clock Source */
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) {
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}
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#else
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#error "CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL not selected"
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#endif /* CLOCK_STM32_SYSCLK_SRC_PLL */
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#endif /* CONFIG_CPU_CORTEX_M4 */
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/* Set systick to 1ms */
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SysTick_Config(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000);
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/* Update CMSIS variable */
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SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
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return 0;
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}
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/**
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* @brief RCC device, note that priority is intentionally set to 1 so
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* that the device init runs just after SOC init
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*/
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DEVICE_AND_API_INIT(rcc_stm32, STM32_CLOCK_CONTROL_NAME,
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&stm32_clock_control_init,
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NULL, NULL,
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PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_STM32_DEVICE_INIT_PRIORITY,
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&stm32_clock_control_api);
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