47 lines
1.2 KiB
C
47 lines
1.2 KiB
C
/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_PRIV_H_
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#define ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_PRIV_H_
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#define IDC_REG_SIZE DT_REG_SIZE(DT_INST(0, intel_cavs_idc))
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#define IDC_REG_BASE(x) \
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(DT_REG_ADDR(DT_INST(0, intel_cavs_idc)) + x * IDC_REG_SIZE)
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#define IDC_CPU_OFFSET 0x10
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#define REG_IDCTFC(x) (0x0 + x * IDC_CPU_OFFSET)
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#define REG_IDCTEFC(x) (0x4 + x * IDC_CPU_OFFSET)
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#define REG_IDCITC(x) (0x8 + x * IDC_CPU_OFFSET)
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#define REG_IDCIETC(x) (0xc + x * IDC_CPU_OFFSET)
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#define REG_IDCCTL 0x50
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#define REG_IDCTFC_BUSY (1 << 31)
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#define REG_IDCTFC_MSG_MASK 0x7FFFFFFF
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#define REG_IDCTEFC_MSG_MASK 0x3FFFFFFF
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#define REG_IDCITC_BUSY (1 << 31)
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#define REG_IDCITC_MSG_MASK 0x7FFFFFFF
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#define REG_IDCIETC_DONE (1 << 30)
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#define REG_IDCIETC_MSG_MASK 0x3FFFFFFF
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#define REG_IDCCTL_IDCIDIE(x) (0x100 << (x))
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#define REG_IDCCTL_IDCTBIE(x) (0x1 << (x))
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static inline u32_t idc_read(u32_t reg, u32_t core_id)
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{
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return sys_read32(IDC_REG_BASE(core_id) + reg);
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}
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static inline void idc_write(u32_t reg, u32_t core_id, u32_t val)
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{
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sys_write32(val, IDC_REG_BASE(core_id) + reg);
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}
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#endif /* ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_PRIV_H_ */
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