67 lines
1.8 KiB
C
67 lines
1.8 KiB
C
/*
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* Copyright (c) 2023 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <xtensa/config/core-isa.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/arch/xtensa/xtensa_mmu.h>
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#include <zephyr/sys/util.h>
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#include "../../arch/xtensa/core/include/xtensa_mmu_priv.h"
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const struct xtensa_mmu_range xtensa_soc_mmu_ranges[] = {
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{
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.start = (uint32_t)XCHAL_VECBASE_RESET_VADDR,
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.end = (uint32_t)CONFIG_SRAM_OFFSET,
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.attrs = Z_XTENSA_MMU_X | Z_XTENSA_MMU_CACHED_WB,
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.name = "vecbase",
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},
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{
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/* The ROM is 32MB but the address wraps around back to 0x00000000.
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* So just skip the last page so we don't have to deal with integer
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* overflow.
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*/
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.start = (uint32_t)DT_REG_ADDR(DT_NODELABEL(rom0)),
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.end = (uint32_t)DT_REG_ADDR(DT_NODELABEL(rom0)) +
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(uint32_t)DT_REG_SIZE(DT_NODELABEL(rom0)),
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.attrs = Z_XTENSA_MMU_X | Z_XTENSA_MMU_CACHED_WB,
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.name = "rom",
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},
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};
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int xtensa_soc_mmu_ranges_num = ARRAY_SIZE(xtensa_soc_mmu_ranges);
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void arch_xtensa_mmu_post_init(bool is_core0)
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{
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uint32_t vecbase;
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ARG_UNUSED(is_core0);
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__asm__ volatile("rsr.vecbase %0" : "=r"(vecbase));
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/* Invalidate any autorefill instr TLBs of VECBASE so we can map it
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* permanently below.
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*/
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xtensa_itlb_vaddr_invalidate((void *)vecbase);
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/* Map VECBASE permanently in instr TLB way 4 so we will always have
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* access to exception handlers. Each way 4 TLB covers 1MB (unless
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* ITLBCFG has been changed before this, which should not have
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* happened).
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*
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* Note that we don't want to map the first 1MB in data TLB as
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* we want to keep page 0 (0x00000000) unmapped to catch null pointer
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* de-references.
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*/
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vecbase = ROUND_DOWN(vecbase, MB(1));
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xtensa_itlb_entry_write_sync(
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Z_XTENSA_PTE(vecbase, Z_XTENSA_KERNEL_RING,
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Z_XTENSA_MMU_X | Z_XTENSA_MMU_CACHED_WT),
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Z_XTENSA_TLB_ENTRY((uint32_t)vecbase, 4));
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}
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