47 lines
880 B
Plaintext
47 lines
880 B
Plaintext
# Copyright (c) 2023 Intel Corporation
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
|
|
if BOARD_INTEL_ADL_CRB || BOARD_INTEL_ADL_RVP
|
|
|
|
config BOARD
|
|
default "intel_adl_crb" if BOARD_INTEL_ADL_CRB
|
|
default "intel_adl_rvp" if BOARD_INTEL_ADL_RVP
|
|
|
|
config BUILD_OUTPUT_STRIPPED
|
|
default y
|
|
|
|
config MP_MAX_NUM_CPUS
|
|
default 2
|
|
|
|
# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
|
|
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
|
default 1900000000 if APIC_TSC_DEADLINE_TIMER
|
|
default 1900000000 if APIC_TIMER_TSC
|
|
default 19200000
|
|
|
|
if APIC_TIMER
|
|
config APIC_TIMER_IRQ
|
|
default 24
|
|
config APIC_TIMER_TSC_M
|
|
default 3
|
|
config APIC_TIMER_TSC_N
|
|
default 249
|
|
endif
|
|
|
|
config ACPI
|
|
default y
|
|
|
|
if ACPI
|
|
config HEAP_MEM_POOL_SIZE
|
|
default 64000000
|
|
config MAIN_STACK_SIZE
|
|
default 320000
|
|
|
|
if SHELL
|
|
config SHELL_STACK_SIZE
|
|
default 320000
|
|
endif # SHELL
|
|
endif # ACPI
|
|
|
|
endif # BOARD_INTEL_ADL_CRB || BOARD_INTEL_ADL_RVP
|