121 lines
3.5 KiB
C
121 lines
3.5 KiB
C
/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/sys/device_mmio.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/pcie/pcie.h>
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#include <soc.h>
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#define UART_IS_IOPORT_ACCESS \
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DT_NODE_HAS_PROP(DT_CHOSEN(zephyr_console), io_mapped)
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#if UART_IS_IOPORT_ACCESS
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/* Legacy I/O Port Access to a NS16550 UART */
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#define IN(reg) sys_in8(reg + DT_REG_ADDR(DT_CHOSEN(zephyr_console)))
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#define OUT(reg, val) sys_out8(val, reg + DT_REG_ADDR(DT_CHOSEN(zephyr_console)))
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#elif defined(X86_SOC_EARLY_SERIAL_PCIDEV)
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/* "Modern" mapping of a UART into a PCI MMIO device. The registers
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* are still bytes, but spaced at a 32 bit stride instead of packed
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* together.
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*/
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static mm_reg_t mmio;
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#define IN(reg) (sys_read32(mmio + reg * 4) & 0xff)
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#define OUT(reg, val) sys_write32((val) & 0xff, mmio + reg * 4)
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#elif defined(X86_SOC_EARLY_SERIAL_MMIO8_ADDR)
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/* Still other devices use a MMIO region containing packed byte
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* registers
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*/
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#ifdef DEVICE_MMIO_IS_IN_RAM
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static mm_reg_t mmio;
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#define BASE mmio
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#else
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#define BASE X86_SOC_EARLY_SERIAL_MMIO8_ADDR
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#endif /* DEVICE_MMIO_IS_IN_RAM */
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#define IN(reg) sys_read8(BASE + reg)
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#define OUT(reg, val) sys_write8(val, BASE + reg)
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#else
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#error "Unsupported configuration"
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#endif
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#define REG_THR 0x00 /* Transmitter holding reg. */
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#define REG_IER 0x01 /* Interrupt enable reg. */
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#define REG_FCR 0x02 /* FIFO control reg. */
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#define REG_LCR 0x03 /* Line control reg. */
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#define REG_MCR 0x04 /* Modem control reg. */
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#define REG_LSR 0x05 /* Line status reg. */
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#define REG_BRDL 0x00 /* Baud rate divisor (LSB) */
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#define REG_BRDH 0x01 /* Baud rate divisor (MSB) */
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#define IER_DISABLE 0x00
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#define LCR_8N1 (BIT(0) | BIT(1))
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#define LCR_DLAB_SELECT BIT(7)
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#define MCR_DTR BIT(0)
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#define MCR_RTS BIT(1)
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#define LSR_THRE BIT(5)
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#define FCR_FIFO BIT(0) /* enable XMIT and RCVR FIFO */
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#define FCR_RCVRCLR BIT(1) /* clear RCVR FIFO */
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#define FCR_XMITCLR BIT(2) /* clear XMIT FIFO */
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#define FCR_FIFO_1 0 /* 1 byte in RCVR FIFO */
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static bool early_serial_init_done;
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static uint32_t suppressed_chars;
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static void serout(int c)
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{
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while ((IN(REG_LSR) & LSR_THRE) == 0) {
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}
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OUT(REG_THR, c);
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}
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int arch_printk_char_out(int c)
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{
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if (!early_serial_init_done) {
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suppressed_chars++;
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return c;
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}
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if (c == '\n') {
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serout('\r');
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}
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serout(c);
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return c;
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}
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void z_x86_early_serial_init(void)
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{
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#if defined(DEVICE_MMIO_IS_IN_RAM) && !UART_IS_IOPORT_ACCESS
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#ifdef X86_SOC_EARLY_SERIAL_PCIDEV
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struct pcie_bar mbar;
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pcie_get_mbar(X86_SOC_EARLY_SERIAL_PCIDEV, 0, &mbar);
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pcie_set_cmd(X86_SOC_EARLY_SERIAL_PCIDEV, PCIE_CONF_CMDSTAT_MEM, true);
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device_map(&mmio, mbar.phys_addr, mbar.size, K_MEM_CACHE_NONE);
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#else
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device_map(&mmio, X86_SOC_EARLY_SERIAL_MMIO8_ADDR, 0x1000, K_MEM_CACHE_NONE);
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#endif
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#endif /* DEVICE_MMIO_IS_IN_RAM */
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OUT(REG_IER, IER_DISABLE); /* Disable interrupts */
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OUT(REG_LCR, LCR_DLAB_SELECT); /* DLAB select */
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OUT(REG_BRDL, 1); /* Baud divisor = 1 */
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OUT(REG_BRDH, 0);
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OUT(REG_LCR, LCR_8N1); /* LCR = 8n1 + DLAB off */
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OUT(REG_MCR, MCR_DTR | MCR_RTS);
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/* Turn on FIFO. Some hardware needs this before transmitting */
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OUT(REG_FCR, FCR_FIFO | FCR_FIFO_1 | FCR_RCVRCLR | FCR_XMITCLR);
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early_serial_init_done = true;
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if (suppressed_chars != 0U) {
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printk("WARNING: %u chars lost before early serial init\n",
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suppressed_chars);
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}
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}
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