94 lines
2.4 KiB
Plaintext
94 lines
2.4 KiB
Plaintext
# Intel64-specific X86 subarchitecture options
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# Copyright (c) 2019 Intel Corp.
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# SPDX-License-Identifier: Apache-2.0
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if X86_64
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config MAIN_STACK_SIZE
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default 8192
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config IDLE_STACK_SIZE
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default 4096
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config ISR_STACK_SIZE
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default 16384
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config TEST_EXTRA_STACK_SIZE
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default 4096
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config SYSTEM_WORKQUEUE_STACK_SIZE
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default 8192
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config X86_EXCEPTION_STACK_SIZE
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int "Size of the exception stack(s)"
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default 4096
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help
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The exception stack(s) (one per CPU) are used both for exception
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processing and early kernel/CPU initialization. They need only
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support limited call-tree depth and must fit into the low core,
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so they are typically smaller than the ISR stacks.
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config X86_EXCEPTION_STACK_TRACE
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bool
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default y
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depends on EXCEPTION_STACK_TRACE
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depends on NO_OPTIMIZATIONS
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help
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Internal config to enable runtime stack traces on fatal exceptions.
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config SCHED_IPI_VECTOR
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int "IDT vector to use for scheduler IPI"
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default 34
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range 33 255
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depends on SMP
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config TLB_IPI_VECTOR
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int "IDT vector to use for TLB shootdown IPI"
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default 35
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range 33 255
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depends on SMP
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# We should really only have to provide one of the following two values,
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# but a bug in the Zephyr SDK for x86 precludes the use of division in
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# the assembler. For now, we require that these values be specified manually,
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# and we check to be sure they're a valid combination in arch.h. yes, ugh.
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config ISR_DEPTH
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int "Maximum IRQ nesting depth"
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default 4
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help
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The more nesting allowed, the more room is required for IRQ stacks.
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config ISR_SUBSTACK_SIZE
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int "Size of ISR substacks"
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default 4096
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help
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Number of bytes from the ISR stack to reserve for each nested IRQ
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level. Must be a multiple of 16 to main stack alignment. Note that
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CONFIG_ISR_SUBSTACK_SIZE * CONFIG_ISR_DEPTH must be equal to
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CONFIG_ISR_STACK_SIZE.
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config X86_STACK_PROTECTION
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bool
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default y if HW_STACK_PROTECTION
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select THREAD_STACK_INFO
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help
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This option leverages the MMU to cause a system fatal error if the
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bounds of the current process stack are overflowed. This is done
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by preceding all stack areas with a 4K guard page.
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config X86_USERSPACE
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bool
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default y if USERSPACE
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select THREAD_STACK_INFO
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help
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This option enables APIs to drop a thread's privileges down to ring 3,
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supporting user-level threads that are protected from each other and
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from crashing the kernel.
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config MP_MAX_NUM_CPUS
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range 1 4
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endif # X86_64
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