zephyr/arch/arm
Gil Pitney 1a5537811f cc32xx: Redefine CMSIS IRQn_Type enum to unsigned int
Previously, calling NVIC_SetPriority(IRQn_Type irqn, ....) with
the NWP interrupt number of 171 caused a hard fault during a
subsequent svc #0 instruction during _Swap().

GNU compiler is generating a bit extension instruction (sxtb) which
converts a positive IRQ value argument to a negative value when
casting to the CMSIS IRQn_Type enum parameter type.

This generates a negative index, which then writes to an SCB
control register instead of NVIC register, causing a hard
fault later on.

This issue only occurs when passing interrupt numbers > 0x80
(eg: 171 (0xab) for the NWP) to the CMSIS NVIC apis.

The solution here is simply to redefine IRQn_Type to be an
unsigned 32 bit integer, while redefining the CMSIS IRQn_Type
enum definitions for interrupts less than zero.

Jira: ZEP-1958

Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2017-08-10 16:46:49 -05:00
..
core arm: armv6-m: Support relocating vector table 2017-08-09 18:13:29 -04:00
include kernel: introduce opaque data type for stacks 2017-08-01 16:43:15 -07:00
soc cc32xx: Redefine CMSIS IRQn_Type enum to unsigned int 2017-08-10 16:46:49 -05:00
Kbuild soc: arm: add Makefiles one level up 2016-04-22 21:33:26 +00:00
Kconfig license: Replace Apache boilerplate with SPDX tag 2017-01-19 03:50:58 +00:00
Makefile build: move qemu definitions to boards 2017-01-10 20:20:47 +00:00
defconfig arm: systick: Some SoCs do not have systick 2016-11-27 19:39:26 +00:00