133 lines
4.7 KiB
C
133 lines
4.7 KiB
C
/*
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* Copyright (c) 2022 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __DAI_PARAMS_INTEL_IPC3_H__
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#define __DAI_PARAMS_INTEL_IPC3_H__
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#include <stdint.h>
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#define DAI_INTEL_IPC3_SSP_FMT_I2S 1 /**< I2S mode */
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#define DAI_INTEL_IPC3_SSP_FMT_RIGHT_J 2 /**< Right Justified mode */
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#define DAI_INTEL_IPC3_SSP_FMT_LEFT_J 3 /**< Left Justified mode */
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#define DAI_INTEL_IPC3_SSP_FMT_DSP_A 4 /**< L data MSB after FRM LRC */
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#define DAI_INTEL_IPC3_SSP_FMT_DSP_B 5 /**< L data MSB during FRM LRC */
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#define DAI_INTEL_IPC3_SSP_FMT_PDM 6 /**< Pulse density modulation */
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#define DAI_INTEL_IPC3_SSP_FMT_CONT (1 << 4) /**< continuous clock */
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#define DAI_INTEL_IPC3_SSP_FMT_GATED (0 << 4) /**< clock is gated */
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#define DAI_INTEL_IPC3_SSP_FMT_NB_NF (0 << 8) /**< normal bit clock + frame */
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#define DAI_INTEL_IPC3_SSP_FMT_NB_IF (2 << 8) /**< normal BCLK + inv FRM */
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#define DAI_INTEL_IPC3_SSP_FMT_IB_NF (3 << 8) /**< invert BCLK + nor FRM */
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#define DAI_INTEL_IPC3_SSP_FMT_IB_IF (4 << 8) /**< invert BCLK + FRM */
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#define DAI_INTEL_IPC3_SSP_FMT_CBP_CFP (0 << 12) /**< codec bclk provider & frame provider */
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#define DAI_INTEL_IPC3_SSP_FMT_CBC_CFP (2 << 12) /**< codec bclk consumer & frame provider */
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#define DAI_INTEL_IPC3_SSP_FMT_CBP_CFC (3 << 12) /**< codec bclk provider & frame consumer */
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#define DAI_INTEL_IPC3_SSP_FMT_CBC_CFC (4 << 12) /**< codec bclk consumer & frame consumer */
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#define DAI_INTEL_IPC3_SSP_FMT_FORMAT_MASK 0x000f
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#define DAI_INTEL_IPC3_SSP_FMT_CLOCK_MASK 0x00f0
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#define DAI_INTEL_IPC3_SSP_FMT_INV_MASK 0x0f00
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#define DAI_INTEL_IPC3_SSP_FMT_CLOCK_PROVIDER_MASK 0xf000
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/*
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* DAI_CONFIG flags. The 4 LSB bits are used for the commands, HW_PARAMS, HW_FREE and PAUSE
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* representing when the IPC is sent. The 4 MSB bits are used to add quirks along with the above
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* commands.
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*/
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#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_CMD_MASK 0xF
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#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_NONE 0 /**< config without stage information */
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#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_HW_PARAMS BIT(0) /**< config during hw_params stage */
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#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_HW_FREE BIT(1) /**< config during hw_free stage */
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/**< DAI_CONFIG sent during pause trigger. Only available ABI 3.20 onwards */
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#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_PAUSE BIT(2)
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#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_QUIRK_SHIFT 4
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#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_QUIRK_MASK (0xF << SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT)
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/*
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* This should be used along with the DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_HW_PARAMS to indicate that
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* pipeline stop/pause and DAI DMA stop/pause should happen in two steps. This change is only
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* available ABI 3.20 onwards.
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*/
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#define DAI_INTEL_IPC3_SSP_CONFIG_FLAGS_2_STEP_STOP BIT(0)
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/* ssc1: TINTE */
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#define DAI_INTEL_IPC3_SSP_QUIRK_TINTE (1 << 0)
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/* ssc1: PINTE */
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#define DAI_INTEL_IPC3_SSP_QUIRK_PINTE (1 << 1)
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/* ssc2: SMTATF */
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#define DAI_INTEL_IPC3_SSP_QUIRK_SMTATF (1 << 2)
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/* ssc2: MMRATF */
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#define DAI_INTEL_IPC3_SSP_QUIRK_MMRATF (1 << 3)
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/* ssc2: PSPSTWFDFD */
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#define DAI_INTEL_IPC3_SSP_QUIRK_PSPSTWFDFD (1 << 4)
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/* ssc2: PSPSRWFDFD */
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#define DAI_INTEL_IPC3_SSP_QUIRK_PSPSRWFDFD (1 << 5)
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/* ssc1: LBM */
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#define DAI_INTEL_IPC3_SSP_QUIRK_LBM (1 << 6)
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/* here is the possibility to define others aux macros */
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#define DAI_INTEL_IPC3_SSP_FRAME_PULSE_WIDTH_MAX 38
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#define DAI_INTEL_IPC3_SSP_SLOT_PADDING_MAX 31
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/* SSP clocks control settings
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*
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* Macros for clks_control field in sof_dai_ssp_params struct.
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*/
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/* mclk 0 disable */
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#define DAI_INTEL_IPC3_SSP_MCLK_0_DISABLE BIT(0)
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/* mclk 1 disable */
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#define DAI_INTEL_IPC3_SSP_MCLK_1_DISABLE BIT(1)
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/* mclk keep active */
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#define DAI_INTEL_IPC3_SSP_CLKCTRL_MCLK_KA BIT(2)
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/* bclk keep active */
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#define DAI_INTEL_IPC3_SSP_CLKCTRL_BCLK_KA BIT(3)
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/* fs keep active */
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#define DAI_INTEL_IPC3_SSP_CLKCTRL_FS_KA BIT(4)
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/* bclk idle */
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#define DAI_INTEL_IPC3_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5)
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/* mclk early start */
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#define DAI_INTEL_IPC3_SSP_CLKCTRL_MCLK_ES BIT(6)
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/* bclk early start */
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#define DAI_INTEL_IPC3_SSP_CLKCTRL_BCLK_ES BIT(7)
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/* SSP Configuration Request - SOF_DAI_SSP_CONFIG */
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struct dai_intel_ipc3_ssp_params {
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uint32_t reserved0;
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uint16_t reserved1;
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uint16_t mclk_id;
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uint32_t mclk_rate; /* mclk frequency in Hz */
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uint32_t fsync_rate; /* fsync frequency in Hz */
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uint32_t bclk_rate; /* bclk frequency in Hz */
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/* TDM */
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uint32_t tdm_slots;
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uint32_t rx_slots;
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uint32_t tx_slots;
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/* data */
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uint32_t sample_valid_bits;
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uint16_t tdm_slot_width;
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uint16_t reserved2; /* alignment */
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/* MCLK */
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uint32_t mclk_direction;
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uint16_t frame_pulse_width;
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uint16_t tdm_per_slot_padding_flag;
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uint32_t clks_control;
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uint32_t quirks;
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uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK
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* will be driven, before sending data
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*/
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} __packed;
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#endif /* __DAI_PARAMS_INTEL_IPC3_H__ */
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