60 lines
1.4 KiB
Plaintext
60 lines
1.4 KiB
Plaintext
# SPDX-License-Identifier: Apache-2.0
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CONFIG_ARM=y
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CONFIG_SOC_SERIES_STM32L4X=y
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CONFIG_SOC_STM32L4R5XX=y
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CONFIG_BOARD_NUCLEO_L4R5ZI=y
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# 120MHz system clock only in 'boost power' mode. DM00310109, section
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# 5.1.7 states that the R1MODE bit must be cleared before system can
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# be 120MHz. This requires an update to the stm32 clock control
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# driver, so default to 80MHz until then.
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# CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
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# 80MHz system clock in 'normal power' mode
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=80000000
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# enable uart driver
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CONFIG_SERIAL=y
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# enable pinmux
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CONFIG_PINMUX=y
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# Enable GPIO
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CONFIG_GPIO=y
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# Clock Configuration
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CONFIG_CLOCK_CONTROL=y
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# Use PLLCLK for SYSCLK
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CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y
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# Use HSI (16MHz) to feed into PLL
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CONFIG_CLOCK_STM32_PLL_SRC_HSI=y
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CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4
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CONFIG_CLOCK_STM32_PLL_P_DIVISOR=7
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CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
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CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
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# Produce 80MHz clock at PLLCLK output
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CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=40
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# Comment out above and uncomment below for 120MHz. Note that you
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# must have configured the mcu for boost power mode.
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# CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=60
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# Produce Max (80MHz or 120MHz) HCLK
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CONFIG_CLOCK_STM32_AHB_PRESCALER=1
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# Produce Max (80MHz or 120MHz) APB1 clocks and APB2 clocks
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CONFIG_CLOCK_STM32_APB1_PRESCALER=1
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CONFIG_CLOCK_STM32_APB2_PRESCALER=1
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# Console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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# Enable MPU
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CONFIG_ARM_MPU=y
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