1126bbdca0
The psoc6 SoC has 2 cores, each with different allowed priority ranges: CM0: 0-3 (2 bits of NVIC prio, no prio reserved by the kernel) CM4: 0-6 (3 bits of NVIC prio, one level reserved by the kernel) Since some of the peripherals are only available to the CM4, those should be set to a priority that is actually valid for it. In this case the lowest possible one is 6, so transition from 7 to 6. Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no> |
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| .. | ||
| pinctrl_cypress_psoc6.h | ||
| psoc6-pinctrl.dtsi | ||
| psoc6.dtsi | ||
| psoc6_cm0.dtsi | ||
| psoc6_cm4.dtsi | ||