270 lines
8.8 KiB
C
270 lines
8.8 KiB
C
/*
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* Copyright 2020 Broadcom
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_
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#define ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_
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#include <zephyr/types.h>
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#include <device.h>
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#include <sys/atomic.h>
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/* Cache and Share ability for ITS & Redistributor LPI state tables */
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#define GIC_BASER_CACHE_NGNRNE 0x0UL /* Device-nGnRnE */
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#define GIC_BASER_CACHE_INNERLIKE 0x0UL /* Same as Inner Cacheability. */
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#define GIC_BASER_CACHE_NCACHEABLE 0x1UL /* Non-cacheable */
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#define GIC_BASER_CACHE_RAWT 0x2UL /* Cacheable R-allocate, W-through */
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#define GIC_BASER_CACHE_RAWB 0x3UL /* Cacheable R-allocate, W-back */
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#define GIC_BASER_CACHE_WAWT 0x4UL /* Cacheable W-allocate, W-through */
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#define GIC_BASER_CACHE_WAWB 0x5UL /* Cacheable W-allocate, W-back */
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#define GIC_BASER_CACHE_RAWAWT 0x6UL /* Cacheable R-allocate, W-allocate, W-through */
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#define GIC_BASER_CACHE_RAWAWB 0x7UL /* Cacheable R-allocate, W-allocate, W-back */
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#define GIC_BASER_SHARE_NO 0x0UL /* Non-shareable */
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#define GIC_BASER_SHARE_INNER 0x1UL /* Inner Shareable */
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#define GIC_BASER_SHARE_OUTER 0x2UL /* Outer Shareable */
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/*
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* GIC Register Interface Base Addresses
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*/
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#define GIC_RDIST_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1)
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/* SGI base is at 64K offset from Redistributor */
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#define GICR_SGI_BASE_OFF 0x10000
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/* GICR registers offset from RD_base(n) */
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#define GICR_CTLR 0x0000
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#define GICR_IIDR 0x0004
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#define GICR_TYPER 0x0008
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#define GICR_STATUSR 0x0010
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#define GICR_WAKER 0x0014
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#define GICR_PROPBASER 0x0070
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#define GICR_PENDBASER 0x0078
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/* Register bit definations */
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/* GICD_CTLR Interrupt group definitions */
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#define GICD_CTLR_ENABLE_G0 0
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#define GICD_CTLR_ENABLE_G1NS 1
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#define GICD_CTLR_ENABLE_G1S 2
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#define GICD_CTRL_ARE_S 4
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#define GICD_CTRL_ARE_NS 5
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#define GICD_CTRL_NS 6
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#define GICD_CGRL_E1NWF 7
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/* GICD_CTLR Register write progress bit */
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#define GICD_CTLR_RWP 31
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/* GICR_CTLR */
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#define GICR_CTLR_ENABLE_LPIS BIT(0)
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#define GICR_CTLR_RWP 3
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/* GICR_TYPER */
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#define GICR_TYPER_PROCESSOR_NUMBER_SHIFT 8
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#define GICR_TYPER_PROCESSOR_NUMBER_MASK 0xFFFFUL
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#define GICR_TYPER_PROCESSOR_NUMBER_GET(_val) MASK_GET(_val, GICR_TYPER_PROCESSOR_NUMBER)
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/* GICR_WAKER */
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#define GICR_WAKER_PS 1
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#define GICR_WAKER_CA 2
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/* GICR_PROPBASER */
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#define GITR_PROPBASER_ID_BITS_MASK 0x1fUL
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#define GITR_PROPBASER_INNER_CACHE_SHIFT 7
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#define GITR_PROPBASER_INNER_CACHE_MASK 0x7UL
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#define GITR_PROPBASER_SHAREABILITY_SHIFT 10
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#define GITR_PROPBASER_SHAREABILITY_MASK 0x3UL
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#define GITR_PROPBASER_ADDR_SHIFT 12
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#define GITR_PROPBASER_ADDR_MASK 0xFFFFFFFFFFUL
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#define GITR_PROPBASER_OUTER_CACHE_SHIFT 56
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#define GITR_PROPBASER_OUTER_CACHE_MASK 0x7UL
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/* GICR_PENDBASER */
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#define GITR_PENDBASER_INNER_CACHE_SHIFT 7
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#define GITR_PENDBASER_INNER_CACHE_MASK 0x7UL
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#define GITR_PENDBASER_SHAREABILITY_SHIFT 10
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#define GITR_PENDBASER_SHAREABILITY_MASK 0x3UL
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#define GITR_PENDBASER_ADDR_SHIFT 16
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#define GITR_PENDBASER_ADDR_MASK 0xFFFFFFFFFUL
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#define GITR_PENDBASER_OUTER_CACHE_SHIFT 56
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#define GITR_PENDBASER_OUTER_CACHE_MASK 0x7UL
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#define GITR_PENDBASER_PTZ BIT64(62)
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/* GITCD_IROUTER */
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#define GIC_DIST_IROUTER 0x6000
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#define IROUTER(base, n) (base + GIC_DIST_IROUTER + (n) * 8)
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/*
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* ITS registers, offsets from ITS_base
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*/
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#define GITS_CTLR 0x0000
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#define GITS_IIDR 0x0004
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#define GITS_TYPER 0x0008
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#define GITS_STATUSR 0x0040
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#define GITS_UMSIR 0x0048
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#define GITS_CBASER 0x0080
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#define GITS_CWRITER 0x0088
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#define GITS_CREADR 0x0090
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#define GITS_BASER(n) (0x0100 + ((n) * 8))
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#define GITS_TRANSLATER 0x10040
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/* ITS CTLR register */
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#define GITS_CTLR_ENABLED_SHIFT 0
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#define GITS_CTLR_ENABLED_MASK 0x1UL
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#define GITS_CTLR_ITS_NUMBER_SHIFT 4
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#define GITS_CTLR_ITS_NUMBER_MASK 0xfUL
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#define GITS_CTLR_QUIESCENT_SHIFT 31
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#define GITS_CTLR_QUIESCENT_MASK 0x1UL
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#define GITS_CTLR_ENABLED_GET(_val) MASK_GET(_val, GITS_CTLR_ENABLED)
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#define GITS_CTLR_QUIESCENT_GET(_val) MASK_GET(_val, GITS_CTLR_QUIESCENT)
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/* ITS TYPER register */
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#define GITS_TYPER_PHY_SHIFT 0
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#define GITS_TYPER_PHY_MASK 0x1UL
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#define GITS_TYPER_VIRT_SHIFT 1
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#define GITS_TYPER_VIRT_MASK 0x1UL
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#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4
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#define GITS_TYPER_ITT_ENTRY_SIZE_MASK 0xfUL
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#define GITS_TYPER_IDBITS_SHIFT 8
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#define GITS_TYPER_IDBITS_MASK 0x1fUL
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#define GITS_TYPER_DEVBITS_SHIFT 13
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#define GITS_TYPER_DEVBITS_MASK 0x1fUL
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#define GITS_TYPER_SEIS_SHIFT 18
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#define GITS_TYPER_SEIS_MASK 0x1UL
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#define GITS_TYPER_PTA_SHIFT 19
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#define GITS_TYPER_PTA_MASK 0x1UL
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#define GITS_TYPER_HCC_SHIFT 24
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#define GITS_TYPER_HCC_MASK 0xffUL
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#define GITS_TYPER_CIDBITS_SHIFT 32
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#define GITS_TYPER_CIDBITS_MASK 0xfUL
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#define GITS_TYPER_CIL_SHIFT 36
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#define GITS_TYPER_CIL_MASK 0x1UL
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#define GITS_TYPER_ITT_ENTRY_SIZE_GET(_val) MASK_GET(_val, GITS_TYPER_ITT_ENTRY_SIZE)
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#define GITS_TYPER_PTA_GET(_val) MASK_GET(_val, GITS_TYPER_PTA)
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#define GITS_TYPER_HCC_GET(_val) MASK_GET(_val, GITS_TYPER_HCC)
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#define GITS_TYPER_DEVBITS_GET(_val) MASK_GET(_val, GITS_TYPER_DEVBITS)
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/* ITS COMMON BASER / CBASER register */
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/* ITS CBASER register */
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#define GITS_CBASER_SIZE_SHIFT 0
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#define GITS_CBASER_SIZE_MASK 0xffUL
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#define GITS_CBASER_SHAREABILITY_SHIFT 10
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#define GITS_CBASER_SHAREABILITY_MASK 0x3UL
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#define GITS_CBASER_ADDR_SHIFT 12
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#define GITS_CBASER_ADDR_MASK 0xfffffffffUL
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#define GITS_CBASER_OUTER_CACHE_SHIFT 53
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#define GITS_CBASER_OUTER_CACHE_MASK 0x7UL
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#define GITS_CBASER_INNER_CACHE_SHIFT 59
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#define GITS_CBASER_INNER_CACHE_MASK 0x7UL
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#define GITS_CBASER_VALID_SHIFT 63
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#define GITS_CBASER_VALID_MASK 0x1UL
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/* ITS BASER<n> register */
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#define GITS_BASER_SIZE_SHIFT 0
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#define GITS_BASER_SIZE_MASK 0xffUL
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#define GITS_BASER_PAGE_SIZE_SHIFT 8
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#define GITS_BASER_PAGE_SIZE_MASK 0x3UL
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#define GITS_BASER_PAGE_SIZE_4K 0
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#define GITS_BASER_PAGE_SIZE_16K 1
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#define GITS_BASER_PAGE_SIZE_64K 2
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#define GITS_BASER_SHAREABILITY_SHIFT 10
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#define GITS_BASER_SHAREABILITY_MASK 0x3UL
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#define GITS_BASER_ADDR_SHIFT 12
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#define GITS_BASER_ADDR_MASK 0xfffffffff
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#define GITS_BASER_ENTRY_SIZE_SHIFT 48
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#define GITS_BASER_ENTRY_SIZE_MASK 0x1fUL
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#define GITS_BASER_OUTER_CACHE_SHIFT 53
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#define GITS_BASER_OUTER_CACHE_MASK 0x7UL
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#define GITS_BASER_TYPE_SHIFT 56
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#define GITS_BASER_TYPE_MASK 0x7UL
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#define GITS_BASER_INNER_CACHE_SHIFT 59
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#define GITS_BASER_INNER_CACHE_MASK 0x7UL
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#define GITS_BASER_INDIRECT_SHIFT 62
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#define GITS_BASER_INDIRECT_MASK 0x1UL
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#define GITS_BASER_VALID_SHIFT 63
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#define GITS_BASER_VALID_MASK 0x1UL
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#define GITS_BASER_TYPE_NONE 0
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#define GITS_BASER_TYPE_DEVICE 1
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#define GITS_BASER_TYPE_COLLECTION 4
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#define GITS_BASER_TYPE_GET(_val) MASK_GET(_val, GITS_BASER_TYPE)
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#define GITS_BASER_PAGE_SIZE_GET(_val) MASK_GET(_val, GITS_BASER_PAGE_SIZE)
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#define GITS_BASER_ENTRY_SIZE_GET(_val) MASK_GET(_val, GITS_BASER_ENTRY_SIZE)
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#define GITS_BASER_INDIRECT_GET(_val) MASK_GET(_val, GITS_BASER_INDIRECT)
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#define GITS_BASER_NR_REGS 8
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/* ITS Commands */
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#define GITS_CMD_ID_MOVI 0x01
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#define GITS_CMD_ID_INT 0x03
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#define GITS_CMD_ID_CLEAR 0x04
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#define GITS_CMD_ID_SYNC 0x05
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#define GITS_CMD_ID_MAPD 0x08
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#define GITS_CMD_ID_MAPC 0x09
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#define GITS_CMD_ID_MAPTI 0x0a
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#define GITS_CMD_ID_MAPI 0x0b
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#define GITS_CMD_ID_INV 0x0c
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#define GITS_CMD_ID_INVALL 0x0d
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#define GITS_CMD_ID_MOVALL 0x0e
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#define GITS_CMD_ID_DISCARD 0x0f
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#define GITS_CMD_ID_OFFSET 0
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#define GITS_CMD_ID_SHIFT 0
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#define GITS_CMD_ID_MASK 0xffUL
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#define GITS_CMD_DEVICEID_OFFSET 0
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#define GITS_CMD_DEVICEID_SHIFT 32
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#define GITS_CMD_DEVICEID_MASK 0xffffffffUL
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#define GITS_CMD_SIZE_OFFSET 1
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#define GITS_CMD_SIZE_SHIFT 0
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#define GITS_CMD_SIZE_MASK 0x1fUL
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#define GITS_CMD_EVENTID_OFFSET 1
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#define GITS_CMD_EVENTID_SHIFT 0
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#define GITS_CMD_EVENTID_MASK 0xffffffffUL
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#define GITS_CMD_PINTID_OFFSET 1
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#define GITS_CMD_PINTID_SHIFT 32
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#define GITS_CMD_PINTID_MASK 0xffffffffUL
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#define GITS_CMD_ICID_OFFSET 2
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#define GITS_CMD_ICID_SHIFT 0
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#define GITS_CMD_ICID_MASK 0xffffUL
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#define GITS_CMD_ITTADDR_OFFSET 2
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#define GITS_CMD_ITTADDR_SHIFT 8
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#define GITS_CMD_ITTADDR_MASK 0xffffffffffUL
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#define GITS_CMD_ITTADDR_ALIGN GITS_CMD_ITTADDR_SHIFT
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#define GITS_CMD_ITTADDR_ALIGN_SZ (BIT(0) << GITS_CMD_ITTADDR_ALIGN)
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#define GITS_CMD_RDBASE_OFFSET 2
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#define GITS_CMD_RDBASE_SHIFT 16
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#define GITS_CMD_RDBASE_MASK 0xffffffffUL
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#define GITS_CMD_RDBASE_ALIGN GITS_CMD_RDBASE_SHIFT
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#define GITS_CMD_VALID_OFFSET 2
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#define GITS_CMD_VALID_SHIFT 63
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#define GITS_CMD_VALID_MASK 0x1UL
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#define MASK(__basename) (__basename##_MASK << __basename##_SHIFT)
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#define MASK_SET(__val, __basename) (((__val) & __basename##_MASK) << __basename##_SHIFT)
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#define MASK_GET(__reg, __basename) (((__reg) >> __basename##_SHIFT) & __basename##_MASK)
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#ifdef CONFIG_GIC_V3_ITS
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void its_rdist_map(void);
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void its_rdist_invall(void);
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extern atomic_t nlpi_intid;
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#endif
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#endif /* ZEPHYR_INCLUDE_DRIVERS_INTC_GICV3_PRIV_H_ */
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