482 lines
14 KiB
C
482 lines
14 KiB
C
/*
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* Copyright (c) 2021 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nuvoton_nct38xx_gpio_port
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#include <drivers/gpio.h>
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#include "gpio_nct38xx.h"
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#include "gpio_utils.h"
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#include <logging/log.h>
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LOG_MODULE_DECLARE(gpio_ntc38xx, CONFIG_GPIO_LOG_LEVEL);
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/* Driver config */
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struct gpio_nct38xx_port_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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/* NCT38XX controller dev */
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const struct device *nct38xx_dev;
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/* GPIO port index */
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uint8_t gpio_port;
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/* GPIO port 0 pinmux mask */
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uint8_t pinmux_mask;
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};
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/* Driver data */
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struct gpio_nct38xx_port_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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/* GPIO callback list */
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sys_slist_t cb_list_gpio;
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/* lock GPIO register access */
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struct k_sem lock;
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};
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/* Driver convenience defines */
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#define DRV_CONFIG(dev) ((const struct gpio_nct38xx_port_config *)(dev)->config)
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#define DRV_DATA(dev) ((struct gpio_nct38xx_port_data *)(dev)->data)
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/* GPIO api functions */
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static int gpio_nct38xx_pin_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const struct gpio_nct38xx_port_config *const config = DRV_CONFIG(dev);
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struct gpio_nct38xx_port_data *const data = DRV_DATA(dev);
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uint32_t mask = BIT(pin);
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uint8_t reg, new_reg;
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int ret;
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/* Don't support simultaneous in/out mode */
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if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
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return -ENOTSUP;
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}
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/* Don't support "open source" mode */
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if (((flags & GPIO_SINGLE_ENDED) != 0) && ((flags & GPIO_LINE_OPEN_DRAIN) == 0)) {
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return -ENOTSUP;
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}
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/* Don't support pull-up/pull-down */
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if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
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return -ENOTSUP;
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}
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k_sem_take(&data->lock, K_FOREVER);
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/* Pin multiplexing */
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if (config->gpio_port == 0) {
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ret = nct38xx_reg_read_byte(config->nct38xx_dev, NCT38XX_REG_MUX_CONTROL, ®);
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if (ret < 0) {
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goto done;
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}
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new_reg = reg | mask;
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/* NCT3807 bit3 should be set to 0 */
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new_reg &= config->pinmux_mask;
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ret = nct38xx_reg_update(config->nct38xx_dev, NCT38XX_REG_MUX_CONTROL, reg,
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new_reg);
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if (ret < 0) {
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goto done;
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}
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}
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/* Configure pin as input. */
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if (flags & GPIO_INPUT) {
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ret = nct38xx_reg_read_byte(config->nct38xx_dev,
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NCT38XX_REG_GPIO_DIR(config->gpio_port), ®);
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if (ret < 0) {
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goto done;
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}
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new_reg = reg & ~mask;
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ret = nct38xx_reg_update(config->nct38xx_dev,
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NCT38XX_REG_GPIO_DIR(config->gpio_port), reg, new_reg);
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k_sem_give(&data->lock);
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return ret;
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}
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/* Select open drain 0:push-pull 1:open-drain */
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ret = nct38xx_reg_read_byte(config->nct38xx_dev, NCT38XX_REG_GPIO_OD_SEL(config->gpio_port),
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®);
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if (ret < 0) {
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goto done;
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}
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if (flags & GPIO_OPEN_DRAIN) {
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new_reg = reg | mask;
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} else {
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new_reg = reg & ~mask;
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}
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ret = nct38xx_reg_update(config->nct38xx_dev, NCT38XX_REG_GPIO_OD_SEL(config->gpio_port),
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reg, new_reg);
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if (ret < 0) {
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goto done;
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}
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/* Set level 0:low 1:high */
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nct38xx_reg_read_byte(config->nct38xx_dev, NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port),
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®);
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if (ret < 0) {
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goto done;
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}
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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new_reg = reg | mask;
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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new_reg = reg & ~mask;
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}
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ret = nct38xx_reg_update(config->nct38xx_dev, NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port),
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reg, new_reg);
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if (ret < 0) {
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goto done;
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}
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/* Configure pin as output, if requested 0:input 1:output */
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if (flags & GPIO_OUTPUT) {
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nct38xx_reg_read_byte(config->nct38xx_dev, NCT38XX_REG_GPIO_DIR(config->gpio_port),
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®);
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if (ret < 0) {
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goto done;
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}
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new_reg = reg | mask;
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ret = nct38xx_reg_update(config->nct38xx_dev,
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NCT38XX_REG_GPIO_DIR(config->gpio_port), reg, new_reg);
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}
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done:
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k_sem_give(&data->lock);
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return ret;
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}
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static int gpio_nct38xx_port_get_raw(const struct device *dev, gpio_port_value_t *value)
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{
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const struct gpio_nct38xx_port_config *const config = DRV_CONFIG(dev);
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return nct38xx_reg_read_byte(config->nct38xx_dev,
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NCT38XX_REG_GPIO_DATA_IN(config->gpio_port), (uint8_t *)value);
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}
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static int gpio_nct38xx_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_nct38xx_port_config *const config = DRV_CONFIG(dev);
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struct gpio_nct38xx_port_data *const data = DRV_DATA(dev);
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uint8_t reg, new_reg;
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int ret;
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k_sem_take(&data->lock, K_FOREVER);
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ret = nct38xx_reg_read_byte(config->nct38xx_dev,
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NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port), ®);
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if (ret < 0) {
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goto done;
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}
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new_reg = ((reg & ~mask) | (value & mask));
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ret = nct38xx_reg_update(config->nct38xx_dev, NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port),
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reg, new_reg);
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done:
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k_sem_give(&data->lock);
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return ret;
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}
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static int gpio_nct38xx_port_set_bits_raw(const struct device *dev, gpio_port_pins_t mask)
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{
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const struct gpio_nct38xx_port_config *const config = DRV_CONFIG(dev);
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struct gpio_nct38xx_port_data *const data = DRV_DATA(dev);
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uint8_t reg, new_reg;
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int ret;
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k_sem_take(&data->lock, K_FOREVER);
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ret = nct38xx_reg_read_byte(config->nct38xx_dev,
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NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port), ®);
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if (ret < 0) {
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goto done;
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}
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new_reg = reg | mask;
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ret = nct38xx_reg_update(config->nct38xx_dev, NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port),
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reg, new_reg);
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done:
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k_sem_give(&data->lock);
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return ret;
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}
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static int gpio_nct38xx_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t mask)
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{
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const struct gpio_nct38xx_port_config *const config = DRV_CONFIG(dev);
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struct gpio_nct38xx_port_data *const data = DRV_DATA(dev);
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uint8_t reg, new_reg;
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int ret;
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k_sem_take(&data->lock, K_FOREVER);
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ret = nct38xx_reg_read_byte(config->nct38xx_dev,
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NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port), ®);
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if (ret < 0) {
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goto done;
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}
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new_reg = reg & ~mask;
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ret = nct38xx_reg_update(config->nct38xx_dev, NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port),
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reg, new_reg);
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done:
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k_sem_give(&data->lock);
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return ret;
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}
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static int gpio_nct38xx_port_toggle_bits(const struct device *dev, gpio_port_pins_t mask)
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{
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const struct gpio_nct38xx_port_config *const config = DRV_CONFIG(dev);
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struct gpio_nct38xx_port_data *const data = DRV_DATA(dev);
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uint8_t reg, new_reg;
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int ret;
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k_sem_take(&data->lock, K_FOREVER);
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ret = nct38xx_reg_read_byte(config->nct38xx_dev,
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NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port), ®);
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if (ret < 0) {
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goto done;
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}
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new_reg = reg ^ mask;
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ret = nct38xx_reg_update(config->nct38xx_dev, NCT38XX_REG_GPIO_DATA_OUT(config->gpio_port),
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reg, new_reg);
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done:
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k_sem_give(&data->lock);
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return ret;
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}
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static int gpio_nct38xx_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
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enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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const struct gpio_nct38xx_port_config *const config = DRV_CONFIG(dev);
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struct gpio_nct38xx_port_data *const data = DRV_DATA(dev);
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uint8_t reg, new_reg, rise, new_rise, fall, new_fall;
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int ret;
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uint32_t mask = BIT(pin);
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k_sem_take(&data->lock, K_FOREVER);
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/* Disable irq before configuring them */
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ret = nct38xx_reg_read_byte(config->nct38xx_dev,
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NCT38XX_REG_GPIO_ALERT_MASK(config->gpio_port), ®);
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if (ret < 0) {
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goto done;
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}
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new_reg = reg & ~mask;
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ret = nct38xx_reg_update(config->nct38xx_dev,
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NCT38XX_REG_GPIO_ALERT_MASK(config->gpio_port), reg, new_reg);
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if (ret < 0) {
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goto done;
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}
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/* Configure and enable interrupt? */
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if (mode == GPIO_INT_MODE_DISABLED) {
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goto done;
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}
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/* set edge register */
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ret = nct38xx_reg_read_byte(config->nct38xx_dev,
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NCT38XX_REG_GPIO_ALERT_RISE(config->gpio_port), &rise);
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if (ret < 0) {
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goto done;
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}
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ret = nct38xx_reg_read_byte(config->nct38xx_dev,
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NCT38XX_REG_GPIO_ALERT_FALL(config->gpio_port), &fall);
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if (ret < 0) {
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goto done;
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}
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if (mode == GPIO_INT_MODE_EDGE) {
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if (trig == GPIO_INT_TRIG_LOW) {
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new_rise = rise & ~mask;
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new_fall = fall | mask;
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} else if (trig == GPIO_INT_TRIG_HIGH) {
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new_rise = rise | mask;
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new_fall = fall & ~mask;
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} else if (trig == GPIO_INT_TRIG_BOTH) {
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new_rise = rise | mask;
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new_fall = fall | mask;
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} else {
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LOG_ERR("Invalid interrupt trigger type %d", trig);
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return -EINVAL;
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}
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} else {
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/* level mode */
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new_rise = rise & ~mask;
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new_fall = fall & ~mask;
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}
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ret = nct38xx_reg_update(config->nct38xx_dev,
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NCT38XX_REG_GPIO_ALERT_RISE(config->gpio_port), rise, new_rise);
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if (ret < 0) {
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goto done;
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}
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ret = nct38xx_reg_update(config->nct38xx_dev,
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NCT38XX_REG_GPIO_ALERT_FALL(config->gpio_port), fall, new_fall);
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if (ret < 0) {
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goto done;
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}
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if (mode == GPIO_INT_MODE_LEVEL) {
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/* set active high/low */
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ret = nct38xx_reg_read_byte(config->nct38xx_dev,
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NCT38XX_REG_GPIO_ALERT_LEVEL(config->gpio_port), ®);
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if (ret < 0) {
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goto done;
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}
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if (trig == GPIO_INT_TRIG_LOW) {
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new_reg = reg & ~mask;
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} else if (trig == GPIO_INT_TRIG_HIGH) {
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new_reg = reg | mask;
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} else {
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LOG_ERR("Invalid interrupt trigger type %d", trig);
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ret = -EINVAL;
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goto done;
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}
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ret = nct38xx_reg_update(config->nct38xx_dev,
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NCT38XX_REG_GPIO_ALERT_LEVEL(config->gpio_port), reg,
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new_reg);
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if (ret < 0) {
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goto done;
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}
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}
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/* Clear pending bit */
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ret = nct38xx_reg_write_byte(config->nct38xx_dev,
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NCT38XX_REG_GPIO_ALERT_STAT(config->gpio_port), mask);
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if (ret < 0) {
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goto done;
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}
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/* Enable it after configuration is completed */
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ret = nct38xx_reg_read_byte(config->nct38xx_dev,
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NCT38XX_REG_GPIO_ALERT_MASK(config->gpio_port), ®);
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if (ret < 0) {
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goto done;
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}
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new_reg = reg | mask;
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ret = nct38xx_reg_update(config->nct38xx_dev,
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NCT38XX_REG_GPIO_ALERT_MASK(config->gpio_port), reg, new_reg);
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done:
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k_sem_give(&data->lock);
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return ret;
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}
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static int gpio_nct38xx_manage_callback(const struct device *dev, struct gpio_callback *callback,
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bool set)
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{
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struct gpio_nct38xx_port_data *const data = DRV_DATA(dev);
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return gpio_manage_callback(&data->cb_list_gpio, callback, set);
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}
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int gpio_nct38xx_dispatch_port_isr(const struct device *dev)
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{
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const struct gpio_nct38xx_port_config *const config = DRV_CONFIG(dev);
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struct gpio_nct38xx_port_data *const data = DRV_DATA(dev);
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uint8_t alert_pins, mask;
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int ret;
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do {
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k_sem_take(&data->lock, K_FOREVER);
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ret = nct38xx_reg_read_byte(config->nct38xx_dev,
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NCT38XX_REG_GPIO_ALERT_STAT(config->gpio_port),
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&alert_pins);
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if (ret < 0) {
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k_sem_give(&data->lock);
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return ret;
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}
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ret = nct38xx_reg_read_byte(config->nct38xx_dev,
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NCT38XX_REG_GPIO_ALERT_MASK(config->gpio_port), &mask);
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if (ret < 0) {
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k_sem_give(&data->lock);
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return ret;
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}
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alert_pins &= mask;
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if (alert_pins) {
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ret = nct38xx_reg_write_byte(config->nct38xx_dev,
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NCT38XX_REG_GPIO_ALERT_STAT(config->gpio_port),
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alert_pins);
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if (ret < 0) {
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k_sem_give(&data->lock);
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return ret;
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}
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}
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k_sem_give(&data->lock);
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gpio_fire_callbacks(&data->cb_list_gpio, dev, alert_pins);
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/*
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* Vendor defined alert is generated if at least one STATn bit
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* changes from 0 to 1. We should guarantee the STATn bit is
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* clear to 0 before leaving isr.
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*/
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} while (alert_pins);
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return 0;
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}
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static const struct gpio_driver_api gpio_nct38xx_driver = {
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.pin_configure = gpio_nct38xx_pin_config,
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.port_get_raw = gpio_nct38xx_port_get_raw,
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.port_set_masked_raw = gpio_nct38xx_port_set_masked_raw,
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.port_set_bits_raw = gpio_nct38xx_port_set_bits_raw,
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.port_clear_bits_raw = gpio_nct38xx_port_clear_bits_raw,
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.port_toggle_bits = gpio_nct38xx_port_toggle_bits,
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.pin_interrupt_configure = gpio_nct38xx_pin_interrupt_configure,
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.manage_callback = gpio_nct38xx_manage_callback,
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};
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static int gpio_nct38xx_port_init(const struct device *dev)
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{
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const struct gpio_nct38xx_port_config *const config = DRV_CONFIG(dev);
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struct gpio_nct38xx_port_data *const data = DRV_DATA(dev);
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if (!device_is_ready(config->nct38xx_dev)) {
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LOG_ERR("%s is not ready", config->nct38xx_dev->name);
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return -ENODEV;
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}
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k_sem_init(&data->lock, 1, 1);
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return 0;
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}
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/* NCT38XX GPIO port driver must be initialized after NCT38XX GPIO driver */
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BUILD_ASSERT(CONFIG_GPIO_NCT38XX_PORT_INIT_PRIORITY > CONFIG_GPIO_NCT38XX_INIT_PRIORITY);
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#define GPIO_NCT38XX_PORT_DEVICE_INSTANCE(inst) \
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static const struct gpio_nct38xx_port_config gpio_nct38xx_port_cfg_##inst = { \
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.common = { .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst) & \
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DT_INST_PROP(inst, pin_mask) }, \
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.nct38xx_dev = DEVICE_DT_GET(DT_PARENT(DT_DRV_INST(inst))), \
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.gpio_port = DT_INST_REG_ADDR(inst), \
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.pinmux_mask = COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, pinmux_mask), \
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(DT_INST_PROP(inst, pinmux_mask)), (0)), \
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|
}; \
|
|
BUILD_ASSERT(!(DT_INST_REG_ADDR(inst) == 0 && \
|
|
!(DT_INST_NODE_HAS_PROP(inst, pinmux_mask))), \
|
|
"Port 0 should assign pinmux_mask property."); \
|
|
static struct gpio_nct38xx_port_data gpio_nct38xx_port_data_##inst; \
|
|
DEVICE_DT_INST_DEFINE(inst, gpio_nct38xx_port_init, NULL, &gpio_nct38xx_port_data_##inst, \
|
|
&gpio_nct38xx_port_cfg_##inst, POST_KERNEL, \
|
|
CONFIG_GPIO_NCT38XX_PORT_INIT_PRIORITY, &gpio_nct38xx_driver);
|
|
|
|
DT_INST_FOREACH_STATUS_OKAY(GPIO_NCT38XX_PORT_DEVICE_INSTANCE)
|