495 lines
12 KiB
C
495 lines
12 KiB
C
/*
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* Copyright (c) 2020 Markus Fuchs <markus.fuchs@de.sauter-bc.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <kernel.h>
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#include <device.h>
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#include <sys/__assert.h>
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#include <crypto/cipher.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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#include <drivers/clock_control.h>
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#include <sys/byteorder.h>
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#include "crypto_stm32_priv.h"
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#define LOG_LEVEL CONFIG_CRYPTO_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(crypto_stm32);
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_cryp)
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#define DT_DRV_COMPAT st_stm32_cryp
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_aes)
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#define DT_DRV_COMPAT st_stm32_aes
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#else
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#error No STM32 HW Crypto Accelerator in device tree
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#endif
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#define CRYP_SUPPORT (CAP_RAW_KEY | CAP_SEPARATE_IO_BUFS | CAP_SYNC_OPS | \
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CAP_NO_IV_PREFIX)
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#define BLOCK_LEN_BYTES 16
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#define BLOCK_LEN_WORDS (BLOCK_LEN_BYTES / sizeof(uint32_t))
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#define CRYPTO_MAX_SESSION CONFIG_CRYPTO_STM32_MAX_SESSION
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#if defined(CRYP_KEYSIZE_192B)
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#define STM32_CRYPTO_KEYSIZE_192B_SUPPORT
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#endif
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_cryp)
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#define STM32_RCC_CRYPTO_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
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#define STM32_RCC_CRYPTO_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
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#define STM32_CRYPTO_TYPEDEF CRYP_TypeDef
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_aes)
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#define STM32_RCC_CRYPTO_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
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#define STM32_RCC_CRYPTO_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
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#define STM32_CRYPTO_TYPEDEF AES_TypeDef
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#endif
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struct crypto_stm32_session crypto_stm32_sessions[CRYPTO_MAX_SESSION];
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static void copy_reverse_words(uint8_t *dst_buf, int dst_len,
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uint8_t *src_buf, int src_len)
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{
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int i;
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__ASSERT_NO_MSG(dst_len >= src_len);
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__ASSERT_NO_MSG((dst_len % 4) == 0);
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memcpy(dst_buf, src_buf, src_len);
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for (i = 0; i < dst_len; i += sizeof(uint32_t)) {
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sys_mem_swap(&dst_buf[i], sizeof(uint32_t));
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}
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}
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static int do_encrypt(struct cipher_ctx *ctx, uint8_t *in_buf, int in_len,
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uint8_t *out_buf)
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{
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HAL_StatusTypeDef status;
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struct crypto_stm32_data *data = CRYPTO_STM32_DATA(ctx->device);
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struct crypto_stm32_session *session = CRYPTO_STM32_SESSN(ctx);
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k_sem_take(&data->device_sem, K_FOREVER);
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status = HAL_CRYP_SetConfig(&data->hcryp, &session->config);
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if (status != HAL_OK) {
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LOG_ERR("Configuration error");
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k_sem_give(&data->device_sem);
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return -EIO;
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}
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status = HAL_CRYP_Encrypt(&data->hcryp, (uint32_t *)in_buf, in_len,
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(uint32_t *)out_buf, HAL_MAX_DELAY);
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if (status != HAL_OK) {
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LOG_ERR("Encryption error");
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k_sem_give(&data->device_sem);
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return -EIO;
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}
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k_sem_give(&data->device_sem);
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return 0;
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}
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static int do_decrypt(struct cipher_ctx *ctx, uint8_t *in_buf, int in_len,
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uint8_t *out_buf)
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{
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HAL_StatusTypeDef status;
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struct crypto_stm32_data *data = CRYPTO_STM32_DATA(ctx->device);
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struct crypto_stm32_session *session = CRYPTO_STM32_SESSN(ctx);
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k_sem_take(&data->device_sem, K_FOREVER);
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status = HAL_CRYP_SetConfig(&data->hcryp, &session->config);
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if (status != HAL_OK) {
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LOG_ERR("Configuration error");
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k_sem_give(&data->device_sem);
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return -EIO;
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}
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status = HAL_CRYP_Decrypt(&data->hcryp, (uint32_t *)in_buf, in_len,
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(uint32_t *)out_buf, HAL_MAX_DELAY);
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if (status != HAL_OK) {
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LOG_ERR("Decryption error");
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k_sem_give(&data->device_sem);
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return -EIO;
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}
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k_sem_give(&data->device_sem);
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return 0;
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}
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static int crypto_stm32_ecb_encrypt(struct cipher_ctx *ctx,
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struct cipher_pkt *pkt)
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{
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int ret;
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/* For security reasons, ECB mode should not be used to encrypt
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* more than one block. Use CBC mode instead.
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*/
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if (pkt->in_len > 16) {
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LOG_ERR("Cannot encrypt more than 1 block");
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return -EINVAL;
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}
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ret = do_encrypt(ctx, pkt->in_buf, pkt->in_len, pkt->out_buf);
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if (ret == 0) {
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pkt->out_len = 16;
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}
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return ret;
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}
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static int crypto_stm32_ecb_decrypt(struct cipher_ctx *ctx,
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struct cipher_pkt *pkt)
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{
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int ret;
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/* For security reasons, ECB mode should not be used to encrypt
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* more than one block. Use CBC mode instead.
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*/
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if (pkt->in_len > 16) {
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LOG_ERR("Cannot encrypt more than 1 block");
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return -EINVAL;
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}
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ret = do_decrypt(ctx, pkt->in_buf, pkt->in_len, pkt->out_buf);
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if (ret == 0) {
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pkt->out_len = 16;
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}
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return ret;
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}
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static int crypto_stm32_cbc_encrypt(struct cipher_ctx *ctx,
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struct cipher_pkt *pkt, uint8_t *iv)
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{
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int ret;
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uint32_t vec[BLOCK_LEN_WORDS];
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int out_offset = 0;
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struct crypto_stm32_session *session = CRYPTO_STM32_SESSN(ctx);
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copy_reverse_words((uint8_t *)vec, sizeof(vec), iv, BLOCK_LEN_BYTES);
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session->config.pInitVect = vec;
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if ((ctx->flags & CAP_NO_IV_PREFIX) == 0U) {
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/* Prefix IV to ciphertext unless CAP_NO_IV_PREFIX is set. */
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memcpy(pkt->out_buf, iv, 16);
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out_offset = 16;
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}
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ret = do_encrypt(ctx, pkt->in_buf, pkt->in_len,
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pkt->out_buf + out_offset);
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if (ret == 0) {
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pkt->out_len = pkt->in_len + out_offset;
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}
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return ret;
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}
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static int crypto_stm32_cbc_decrypt(struct cipher_ctx *ctx,
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struct cipher_pkt *pkt, uint8_t *iv)
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{
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int ret;
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uint32_t vec[BLOCK_LEN_WORDS];
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int in_offset = 0;
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struct crypto_stm32_session *session = CRYPTO_STM32_SESSN(ctx);
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copy_reverse_words((uint8_t *)vec, sizeof(vec), iv, BLOCK_LEN_BYTES);
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session->config.pInitVect = vec;
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if ((ctx->flags & CAP_NO_IV_PREFIX) == 0U) {
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in_offset = 16;
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}
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ret = do_decrypt(ctx, pkt->in_buf + in_offset, pkt->in_len,
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pkt->out_buf);
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if (ret == 0) {
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pkt->out_len = pkt->in_len - in_offset;
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}
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return ret;
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}
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static int crypto_stm32_ctr_encrypt(struct cipher_ctx *ctx,
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struct cipher_pkt *pkt, uint8_t *iv)
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{
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int ret;
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uint32_t ctr[BLOCK_LEN_WORDS] = {0};
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int ivlen = ctx->keylen - (ctx->mode_params.ctr_info.ctr_len >> 3);
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struct crypto_stm32_session *session = CRYPTO_STM32_SESSN(ctx);
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copy_reverse_words((uint8_t *)ctr, sizeof(ctr), iv, ivlen);
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session->config.pInitVect = ctr;
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ret = do_encrypt(ctx, pkt->in_buf, pkt->in_len, pkt->out_buf);
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if (ret == 0) {
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pkt->out_len = pkt->in_len;
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}
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return ret;
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}
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static int crypto_stm32_ctr_decrypt(struct cipher_ctx *ctx,
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struct cipher_pkt *pkt, uint8_t *iv)
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{
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int ret;
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uint32_t ctr[BLOCK_LEN_WORDS] = {0};
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int ivlen = ctx->keylen - (ctx->mode_params.ctr_info.ctr_len >> 3);
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struct crypto_stm32_session *session = CRYPTO_STM32_SESSN(ctx);
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copy_reverse_words((uint8_t *)ctr, sizeof(ctr), iv, ivlen);
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session->config.pInitVect = ctr;
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ret = do_decrypt(ctx, pkt->in_buf, pkt->in_len, pkt->out_buf);
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if (ret == 0) {
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pkt->out_len = pkt->in_len;
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}
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return ret;
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}
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static int crypto_stm32_get_unused_session_index(const struct device *dev)
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{
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int i;
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struct crypto_stm32_data *data = CRYPTO_STM32_DATA(dev);
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k_sem_take(&data->session_sem, K_FOREVER);
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for (i = 0; i < CRYPTO_MAX_SESSION; i++) {
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if (!crypto_stm32_sessions[i].in_use) {
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crypto_stm32_sessions[i].in_use = true;
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k_sem_give(&data->session_sem);
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return i;
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}
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}
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k_sem_give(&data->session_sem);
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return -1;
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}
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static int crypto_stm32_session_setup(const struct device *dev,
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struct cipher_ctx *ctx,
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enum cipher_algo algo,
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enum cipher_mode mode,
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enum cipher_op op_type)
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{
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int ctx_idx;
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struct crypto_stm32_session *session;
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struct crypto_stm32_data *data = CRYPTO_STM32_DATA(dev);
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if (ctx->flags & ~(CRYP_SUPPORT)) {
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LOG_ERR("Unsupported flag");
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return -EINVAL;
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}
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if (algo != CRYPTO_CIPHER_ALGO_AES) {
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LOG_ERR("Unsupported algo");
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return -EINVAL;
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}
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/* The CRYP peripheral supports the AES ECB, CBC, CTR, CCM and GCM
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* modes of operation, of which ECB, CBC, CTR and CCM are supported
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* through the crypto API. However, in CCM mode, although the STM32Cube
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* HAL driver follows the documentation (cf. RM0090, par. 23.3) by
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* padding incomplete input data blocks in software prior encryption,
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* incorrect authentication tags are returned for input data which is
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* not a multiple of 128 bits. Therefore, CCM mode is not supported by
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* this driver.
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*/
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if ((mode != CRYPTO_CIPHER_MODE_ECB) &&
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(mode != CRYPTO_CIPHER_MODE_CBC) &&
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(mode != CRYPTO_CIPHER_MODE_CTR)) {
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LOG_ERR("Unsupported mode");
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return -EINVAL;
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}
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/* The STM32F4 CRYP peripheral supports key sizes of 128, 192 and 256
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* bits.
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*/
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if ((ctx->keylen != 16U) &&
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#if defined(STM32_CRYPTO_KEYSIZE_192B_SUPPORT)
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(ctx->keylen != 24U) &&
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#endif
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(ctx->keylen != 32U)) {
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LOG_ERR("%u key size is not supported", ctx->keylen);
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return -EINVAL;
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}
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ctx_idx = crypto_stm32_get_unused_session_index(dev);
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if (ctx_idx < 0) {
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LOG_ERR("No free session for now");
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return -ENOSPC;
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}
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session = &crypto_stm32_sessions[ctx_idx];
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memset(&session->config, 0, sizeof(session->config));
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if (data->hcryp.State == HAL_CRYP_STATE_RESET) {
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if (HAL_CRYP_Init(&data->hcryp) != HAL_OK) {
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LOG_ERR("Initialization error");
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session->in_use = false;
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return -EIO;
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}
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}
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switch (ctx->keylen) {
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case 16U:
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session->config.KeySize = CRYP_KEYSIZE_128B;
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break;
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#if defined(STM32_CRYPTO_KEYSIZE_192B_SUPPORT)
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case 24U:
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session->config.KeySize = CRYP_KEYSIZE_192B;
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break;
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#endif
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case 32U:
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session->config.KeySize = CRYP_KEYSIZE_256B;
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break;
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}
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if (op_type == CRYPTO_CIPHER_OP_ENCRYPT) {
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switch (mode) {
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case CRYPTO_CIPHER_MODE_ECB:
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session->config.Algorithm = CRYP_AES_ECB;
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ctx->ops.block_crypt_hndlr = crypto_stm32_ecb_encrypt;
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break;
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case CRYPTO_CIPHER_MODE_CBC:
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session->config.Algorithm = CRYP_AES_CBC;
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ctx->ops.cbc_crypt_hndlr = crypto_stm32_cbc_encrypt;
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break;
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case CRYPTO_CIPHER_MODE_CTR:
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session->config.Algorithm = CRYP_AES_CTR;
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ctx->ops.ctr_crypt_hndlr = crypto_stm32_ctr_encrypt;
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break;
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default:
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break;
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}
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} else {
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switch (mode) {
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case CRYPTO_CIPHER_MODE_ECB:
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session->config.Algorithm = CRYP_AES_ECB;
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ctx->ops.block_crypt_hndlr = crypto_stm32_ecb_decrypt;
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break;
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case CRYPTO_CIPHER_MODE_CBC:
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session->config.Algorithm = CRYP_AES_CBC;
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ctx->ops.cbc_crypt_hndlr = crypto_stm32_cbc_decrypt;
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break;
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case CRYPTO_CIPHER_MODE_CTR:
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session->config.Algorithm = CRYP_AES_CTR;
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ctx->ops.ctr_crypt_hndlr = crypto_stm32_ctr_decrypt;
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break;
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default:
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break;
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}
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}
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copy_reverse_words((uint8_t *)session->key, CRYPTO_STM32_AES_MAX_KEY_LEN,
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ctx->key.bit_stream, ctx->keylen);
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session->config.pKey = session->key;
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session->config.DataType = CRYP_DATATYPE_8B;
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session->config.DataWidthUnit = CRYP_DATAWIDTHUNIT_BYTE;
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ctx->drv_sessn_state = session;
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ctx->device = dev;
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return 0;
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}
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static int crypto_stm32_session_free(const struct device *dev,
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struct cipher_ctx *ctx)
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{
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int i;
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struct crypto_stm32_data *data = CRYPTO_STM32_DATA(dev);
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struct crypto_stm32_session *session = CRYPTO_STM32_SESSN(ctx);
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session->in_use = false;
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k_sem_take(&data->session_sem, K_FOREVER);
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/* Disable peripheral only if there are no more active sessions. */
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for (i = 0; i < CRYPTO_MAX_SESSION; i++) {
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if (crypto_stm32_sessions[i].in_use) {
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k_sem_give(&data->session_sem);
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return 0;
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}
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}
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/* Deinitialize and reset peripheral. */
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if (HAL_CRYP_DeInit(&data->hcryp) != HAL_OK) {
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LOG_ERR("Deinitialization error");
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k_sem_give(&data->session_sem);
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return -EIO;
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}
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STM32_RCC_CRYPTO_FORCE_RESET();
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STM32_RCC_CRYPTO_RELEASE_RESET();
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k_sem_give(&data->session_sem);
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return 0;
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}
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static int crypto_stm32_query_caps(const struct device *dev)
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{
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return CRYP_SUPPORT;
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}
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static int crypto_stm32_init(const struct device *dev)
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{
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const struct device *clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
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struct crypto_stm32_data *data = CRYPTO_STM32_DATA(dev);
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const struct crypto_stm32_config *cfg = CRYPTO_STM32_CFG(dev);
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if (clock_control_on(clk, (clock_control_subsys_t *)&cfg->pclken) != 0) {
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LOG_ERR("clock op failed\n");
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return -EIO;
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}
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k_sem_init(&data->device_sem, 1, 1);
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k_sem_init(&data->session_sem, 1, 1);
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if (HAL_CRYP_DeInit(&data->hcryp) != HAL_OK) {
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LOG_ERR("Peripheral reset error");
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return -EIO;
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}
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return 0;
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}
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static struct crypto_driver_api crypto_enc_funcs = {
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.begin_session = crypto_stm32_session_setup,
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.free_session = crypto_stm32_session_free,
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.crypto_async_callback_set = NULL,
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.query_hw_caps = crypto_stm32_query_caps,
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};
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static struct crypto_stm32_data crypto_stm32_dev_data = {
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.hcryp = {
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.Instance = (STM32_CRYPTO_TYPEDEF *)DT_INST_REG_ADDR(0),
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}
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};
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static struct crypto_stm32_config crypto_stm32_dev_config = {
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.pclken = {
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.enr = DT_INST_CLOCKS_CELL(0, bits),
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.bus = DT_INST_CLOCKS_CELL(0, bus)
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}
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};
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DEVICE_DT_INST_DEFINE(0, crypto_stm32_init, NULL,
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&crypto_stm32_dev_data,
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&crypto_stm32_dev_config, POST_KERNEL,
|
|
CONFIG_CRYPTO_INIT_PRIORITY, (void *)&crypto_enc_funcs);
|