112 lines
4.3 KiB
ReStructuredText
112 lines
4.3 KiB
ReStructuredText
.. _litex-vexriscv:
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LiteX VexRiscv
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##############
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LiteX VexRiscv is an example of a system on a chip (SoC) that consists of
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a `VexRiscv processor <https://github.com/SpinalHDL/VexRiscv>`_
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and additional peripherals. This setup has been generated using
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`LiteX SoC Builder <https://github.com/enjoy-digital/litex>`_ and can be used
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on various FPGA chips. The bitstream (FPGA configuration file) can be
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obtained using both vendor-specific tools and open-source tools, including the
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`SymbiFlow toolchain <https://symbiflow.github.io/>`_.
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The ``litex_vexriscv`` board configuration in Zephyr is meant for the
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LiteX VexRiscv SoC implementation generated for the
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`Digilent Arty A7-35T Development Board <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists>`_.
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.. image:: img/litex_vexriscv.jpg
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:width: 650px
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:align: center
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:alt: LiteX VexRiscv on Digilent Arty 35T Board
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LiteX is based on
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`Migen <https://m-labs.hk/gateware/migen/>`_/`MiSoC SoC builder <https://github.com/m-labs/misoc>`_
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and provides ready-made system components such as buses, streams, interconnects,
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common cores, and CPU wrappers to create SoCs easily. The tool contains
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mechanisms for integrating, simulating, and building various designs
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that target multiple chips of different vendors.
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More information about the LiteX project can be found on
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`LiteX's website <https://github.com/enjoy-digital/litex>`_.
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VexRiscv is a 32-bit implementation of the RISC-V CPU architecture
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written in the `SpinalHDL <https://spinalhdl.github.io/SpinalDoc-RTD/>`_.
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The processor supports M, C, and A RISC-V instruction
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set extensions, with numerous optimizations that include multistage
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pipelines and data caching. The project provides many optional extensions
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that can be used to customize the design (JTAG, MMU, MUL/DIV extensions).
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The implementation is optimized for FPGA chips.
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More information about the project can be found on
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`VexRiscv's website <https://github.com/SpinalHDL/VexRiscv>`_.
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LiteX VexRiscv with SymbiFlow
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*****************************
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To run the ZephyrOS on the VexRiscv CPU, it is necessary to prepare the
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bitstream for the FPGA on a Digilent Arty A7-35 Board. This can be achieved
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using the LiteX SoC Builder together with the SymbiFlow toolchain.
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.. image:: img/symbiflow.svg
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:width: 300px
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:align: center
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:alt: SymbiFlow Logo
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SymbiFlow is an Open Source Verilog-to-Bitstream FPGA synthesis flow,
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targeting FPGAs of multiple vendors. Currently, it targets the Xilinx 7-Series,
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Lattice iCE40, Lattice ECP5 FPGAs, QuickLogic EOS S3 and is gradually being
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expanded to provide a comprehensive end-to-end FPGA synthesis flow.
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More information about the project can be found on
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`Symbiflow's website <https://symbiflow.github.io/>`_.
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Bitstream Generation
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====================
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In order to generate the bitstream for the Digilent Arty A7-35 Board, proceed
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with the following instruction:
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1. Install the SymbiFlow toolchain using instruction available in the
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`symbiflow-examples <https://github.com/SymbiFlow/symbiflow-examples>`_ repository.
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#. Install the RISC-V toolchain:
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.. code-block:: bash
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wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
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tar -xf riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14.tar.gz
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export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14/bin/
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#. Download LiteX:
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.. code-block:: bash
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wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
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chmod +x litex_setup.py
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./litex_setup.py init
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./litex_setup.py install
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#. Generate the bitstream:
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.. code-block:: bash
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cd litex/litex/boards/targets && ./arty.py --toolchain symbiflow --cpu-type vexriscv --sys-clk-freq 80e6 --build
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Programming and debugging
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*************************
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Building
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========
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Applications for the ``litex_vexriscv`` board configuration can be built as usual
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(see :ref:`build_an_application`).
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In order to build the application for ``litex_vexriscv``, set the ``BOARD`` variable
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to ``litex_vexriscv``.
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Booting
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=======
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You can boot from a serial port using `flterm: <https://github.com/timvideos/flterm>`_, e.g.:
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.. code-block:: bash
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flterm --port /dev/ttyUSB0 --kernel <path_to_zephyr.bin> --kernel-adr 0x40000000
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