57 lines
2.0 KiB
C
57 lines
2.0 KiB
C
/*
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* Copyright (c) 2016 Open-RnD Sp. z o.o.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _STM32F1_CLOCK_CONTROL_H_
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#define _STM32F1_CLOCK_CONTROL_H_
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/**
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* @file
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*
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* @brief Clock subsystem IDs for STM32F1 family
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*/
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enum {
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/* APB1 */
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STM32F10X_CLOCK_SUBSYS_TIM2 = 1 << 0,
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STM32F10X_CLOCK_SUBSYS_TIM3 = 1 << 1,
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STM32F10X_CLOCK_SUBSYS_TIM4 = 1 << 2,
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STM32F10X_CLOCK_SUBSYS_TIM5 = 1 << 3,
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STM32F10X_CLOCK_SUBSYS_TIM6 = 1 << 4,
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STM32F10X_CLOCK_SUBSYS_TIM7 = 1 << 5,
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STM32F10X_CLOCK_SUBSYS_WWDG = 1 << 11,
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STM32F10X_CLOCK_SUBSYS_SPI2 = 1 << 14,
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STM32F10X_CLOCK_SUBSYS_SPI3 = 1 << 15,
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STM32F10X_CLOCK_SUBSYS_USART2 = 1 << 17,
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STM32F10X_CLOCK_SUBSYS_USART3 = 1 << 18,
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STM32F10X_CLOCK_SUBSYS_UART4 = 1 << 19,
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STM32F10X_CLOCK_SUBSYS_UART5 = 1 << 20,
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STM32F10X_CLOCK_SUBSYS_I2C1 = 1 << 21,
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STM32F10X_CLOCK_SUBSYS_I2C2 = 1 << 22,
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STM32F10X_CLOCK_SUBSYS_CAN1 = 1 << 25,
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STM32F10X_CLOCK_SUBSYS_CAN2 = 1 << 26,
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STM32F10X_CLOCK_SUBSYS_BKP = 1 << 27,
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STM32F10X_CLOCK_SUBSYS_PWR = 1 << 28,
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STM32F10X_CLOCK_SUBSYS_DAC = 1 << 29,
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STM32F10X_CLOCK_APB2_BASE = 1 << 31,
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/* APB2 */
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STM32F10X_CLOCK_SUBSYS_AFIO = STM32F10X_CLOCK_APB2_BASE | 1 << 0,
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STM32F10X_CLOCK_SUBSYS_IOPA = STM32F10X_CLOCK_APB2_BASE | 1 << 2,
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STM32F10X_CLOCK_SUBSYS_IOPB = STM32F10X_CLOCK_APB2_BASE | 1 << 3,
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STM32F10X_CLOCK_SUBSYS_IOPC = STM32F10X_CLOCK_APB2_BASE | 1 << 4,
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STM32F10X_CLOCK_SUBSYS_IOPD = STM32F10X_CLOCK_APB2_BASE | 1 << 5,
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STM32F10X_CLOCK_SUBSYS_IOPE = STM32F10X_CLOCK_APB2_BASE | 1 << 6,
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STM32F10X_CLOCK_SUBSYS_IOPF = STM32F10X_CLOCK_APB2_BASE | 1 << 7,
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STM32F10X_CLOCK_SUBSYS_IOPG = STM32F10X_CLOCK_APB2_BASE | 1 << 8,
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STM32F10X_CLOCK_SUBSYS_ADC1 = STM32F10X_CLOCK_APB2_BASE | 1 << 9,
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STM32F10X_CLOCK_SUBSYS_ADC2 = STM32F10X_CLOCK_APB2_BASE | 1 << 10,
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STM32F10X_CLOCK_SUBSYS_TIM1 = STM32F10X_CLOCK_APB2_BASE | 1 << 11,
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STM32F10X_CLOCK_SUBSYS_SPI1 = STM32F10X_CLOCK_APB2_BASE | 1 << 12,
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STM32F10X_CLOCK_SUBSYS_USART1 = STM32F10X_CLOCK_APB2_BASE | 1 << 14,
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};
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#endif /* _STM32F1_CLOCK_CONTROL_H_ */
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