zephyr/soc/arm/xilinx_zynq7000
Immo Birnbaum a9e935e01b soc: xilinx_zynq7000: fix VBAR, SCTLR contents when coming from u-boot
If a Zephyr binary is booted on the Zynq-7000 not via JTAG download,
but via u-boot's ELF boot function instead, Zephyr will have to revert
certain changes made by u-boot in order to boot properly:

- clear the ICache/DCache enable, branch prediction enable and
  strict alignment enforcement enable bits in the SCTLR register.
  By default, u-boot will also set up the MMU prior to Zephyr
  doing so as well, this can be avoided by changing the u-boot
  build configuration. Therefore, the MMU enable bit is not changed
  at this point.

- set the VBAR register to 0. U-boot moves the interrupt vector
  table to a non-standard location using the VBAR register (no
  change is made by u-boot for SCTLR.V, only VBAR is changed
  to a non-zero memory location).

Without these changes, Zephyr will crash upon the first context
switch at latest, when SVC is invoked and u-boot's vector table
is used rather than the vectors copied to address zero by Zephyr.

In order to perform these changes before coming anwhere near the
MMU / device driver / kernel initialization stages or even the
first context switch, the z_arm_platform_init hook is used, which
is now enabled for the Zynq via the Kconfig.defconfig file.

Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
2022-04-21 13:14:50 +02:00
..
xc7zxxx soc: xilinx_zynq7000: fix VBAR, SCTLR contents when coming from u-boot 2022-04-21 13:14:50 +02:00
xc7zxxxs soc: xilinx_zynq7000: fix VBAR, SCTLR contents when coming from u-boot 2022-04-21 13:14:50 +02:00
CMakeLists.txt
Kconfig
Kconfig.defconfig soc: xilinx_zynq7000: fix VBAR, SCTLR contents when coming from u-boot 2022-04-21 13:14:50 +02:00
Kconfig.soc