Erwan Gouriou 42627d3e25 soc/arm: stm32: All stm32h7 based socs have a cache ... In c5b59282d6, Kconfig option CPU_CORTEX_M_HAS_CACHE was added only to a subset of stm32h7 soc descriptions. There is no reason not to extend to all socs as they all actually feature a cache. Fixes #45073 Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>		2022-04-26 12:06:48 -04:00
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common	soc: stm32: Fix DBGMCU register write for SWO configuration	2022-04-08 15:53:56 -07:00
stm32f0	soc: arm: stm32 adjust wdt timer due to LSI oscillator characteristics	2022-04-08 10:41:55 -05:00
stm32f1	soc: arm: stm32 adjust wdt timer due to LSI oscillator characteristics	2022-04-08 10:41:55 -05:00
stm32f2	…
stm32f3	…
stm32f4	soc: arm: stm32 adjust wdt timer due to LSI oscillator characteristics	2022-04-08 10:41:55 -05:00
stm32f7	arch: arm: aarch32: add Kconfig for arm cortex-m that implements a cache	2022-04-14 16:12:03 -05:00
stm32g0	…
stm32g4	…
stm32h7	soc/arm: stm32: All stm32h7 based socs have a cache	2022-04-26 12:06:48 -04:00
stm32l0	soc: arm: stm32 adjust wdt timer due to LSI oscillator characteristics	2022-04-08 10:41:55 -05:00
stm32l1	soc: arm: stm32 adjust wdt timer due to LSI oscillator characteristics	2022-04-08 10:41:55 -05:00
stm32l4	…
stm32l5	…
stm32mp1	…
stm32u5	…
stm32wb	everywhere: fix typos	2022-03-18 13:24:08 -04:00
stm32wl	…
CMakeLists.txt	…
Kconfig	…
Kconfig.defconfig	…
Kconfig.soc	…