Gerard Marull-Paretas ba0a054e43 boards: riscv: tlsr9518adk80d: fix PWM LED polarity ... The polarity cell was set to '0', but needs to be 'PWM_POLARITY_NORMAL' (LED is driven in active level). Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>		2022-04-24 19:48:49 +02:00
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adp_xc7k_ae350	…
beaglev_starlight_jh7100	…
esp32c3_devkitm	esp32/s2/c3-based boards: remove pinmux definitions	2022-04-20 13:27:47 +02:00
gd32vf103c_starter	dts: pwm: gd,gd32-pwm: add period to PWM cells	2022-04-07 09:35:22 +02:00
gd32vf103v_eval	dts: pwm: gd,gd32-pwm: add period to PWM cells	2022-04-07 09:35:22 +02:00
hifive1	soc: riscv: sifive-freedom: Get coreclk and peripheral clock from DTS.	2022-04-05 12:00:03 +02:00
hifive1_revb	soc: riscv: sifive-freedom: fe310: Support custom coreclk rate in DTS.	2022-04-05 12:00:03 +02:00
hifive_unleashed	soc: riscv: sifive-freedom: Get coreclk and peripheral clock from DTS.	2022-04-05 12:00:03 +02:00
hifive_unmatched	soc: riscv: sifive-freedom: Get coreclk and peripheral clock from DTS.	2022-04-05 12:00:03 +02:00
it8xxx2_evb	ITE boards/it8xxx2_evb/dts: add voltage comparator instance	2022-03-25 15:00:35 -07:00
litex_vexriscv	…
longan_nano	boards: riscv: longan_nano: Add support for TF-Card slot	2022-04-22 09:45:07 +02:00
m2gl025_miv	everywhere: fix typos	2022-03-14 20:22:24 -04:00
neorv32	doc: use :kconfig:option: domain role	2022-03-02 09:28:37 +01:00
qemu_riscv32	soc: riscv: sifive-freedom: Get coreclk and peripheral clock from DTS.	2022-04-05 12:00:03 +02:00
qemu_riscv64	riscv: exception code mega simplification and optimization	2022-03-21 07:28:05 -04:00
rv32m1_vega	boards: riscv: rv32m1_vega: fix PWM period and flags	2022-04-22 10:41:30 -05:00
tlsr9518adk80d	boards: riscv: tlsr9518adk80d: fix PWM LED polarity	2022-04-24 19:48:49 +02:00
index.rst	…