Gerson Fernando Budke f93ee9508b soc: arm: cypress: psoc6: Add Cortex-M0+ int mux support ... PSoC-6 SoC needs that user define the nvic interrupt number to bind with the peripheral interrupt line for the Cortex-M0+ CPU. It uses a multiplex before any NVIC interrupt line. The interrupt vector is selected using interrupt-parent property with the intmux_chN number reference. Note: The PSoC-6 SoC allows that both CPUs receive the same interrupt. A tipical use is GPIO interrupt handle and user is responsable to define interrupt line, priority and take care of enable same peripheral instance on both CPUs only when appropriated. Signed-off-by: Gerson Fernando Budke <gerson.budke@atl-electronics.com>		2021-01-20 17:54:09 -06:00
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cypress_psoc6_dt.h	soc: arm: cypress: psoc6: Add Cortex-M0+ int mux support	2021-01-20 17:54:09 -06:00