170 lines
4.9 KiB
C
170 lines
4.9 KiB
C
/*
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* Copyright (c) 2018 Karsten Koenig
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#ifndef _MCP2515_H_
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#define _MCP2515_H_
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#include <drivers/can.h>
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#define MCP2515_RX_CNT 2
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#define MCP2515_TX_CNT 3
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#define MCP2515_FRAME_LEN 13
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#define DEV_CFG(dev) \
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((const struct mcp2515_config *const)(dev)->config)
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#define DEV_DATA(dev) ((struct mcp2515_data *const)(dev)->data)
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struct mcp2515_tx_cb {
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struct k_sem sem;
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can_tx_callback_t cb;
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void *cb_arg;
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};
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struct mcp2515_data {
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/* spi device data */
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const struct device *spi;
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struct spi_config spi_cfg;
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#if DT_INST_SPI_DEV_HAS_CS_GPIOS(0)
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struct spi_cs_control spi_cs_ctrl;
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#endif /* DT_INST_SPI_DEV_HAS_CS_GPIOS(0) */
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/* interrupt data */
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const struct device *int_gpio;
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struct gpio_callback int_gpio_cb;
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struct k_thread int_thread;
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k_thread_stack_t *int_thread_stack;
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struct k_sem int_sem;
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/* tx data */
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struct k_sem tx_sem;
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struct mcp2515_tx_cb tx_cb[MCP2515_TX_CNT];
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uint8_t tx_busy_map;
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/* filter data */
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uint32_t filter_usage;
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can_rx_callback_t rx_cb[CONFIG_CAN_MAX_FILTER];
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void *cb_arg[CONFIG_CAN_MAX_FILTER];
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struct zcan_filter filter[CONFIG_CAN_MAX_FILTER];
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can_state_change_isr_t state_change_isr;
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/* general data */
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struct k_mutex mutex;
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enum can_state old_state;
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};
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struct mcp2515_config {
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/* spi configuration */
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const char *spi_port;
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uint8_t spi_cs_pin;
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uint8_t spi_cs_flags;
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const char *spi_cs_port;
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uint32_t spi_freq;
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uint8_t spi_slave;
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/* interrupt configuration */
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uint8_t int_pin;
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const char *int_port;
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size_t int_thread_stack_size;
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int int_thread_priority;
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/* CAN timing */
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uint8_t tq_sjw;
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uint8_t tq_prop;
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uint8_t tq_bs1;
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uint8_t tq_bs2;
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uint32_t bus_speed;
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uint32_t osc_freq;
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uint16_t sample_point;
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};
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/*
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* Startup time of 128 OSC1 clock cycles at 1MHz (minimum clock in frequency)
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* see MCP2515 datasheet section 8.1 Oscillator Start-up Timer
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*/
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#define MCP2515_OSC_STARTUP_US 128U
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/* MCP2515 Opcodes */
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#define MCP2515_OPCODE_WRITE 0x02
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#define MCP2515_OPCODE_READ 0x03
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#define MCP2515_OPCODE_BIT_MODIFY 0x05
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#define MCP2515_OPCODE_LOAD_TX_BUFFER 0x40
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#define MCP2515_OPCODE_RTS 0x80
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#define MCP2515_OPCODE_READ_RX_BUFFER 0x90
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#define MCP2515_OPCODE_READ_STATUS 0xA0
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#define MCP2515_OPCODE_RESET 0xC0
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/* MCP2515 Registers */
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#define MCP2515_ADDR_CANSTAT 0x0E
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#define MCP2515_ADDR_CANCTRL 0x0F
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#define MCP2515_ADDR_TEC 0x1C
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#define MCP2515_ADDR_REC 0x1D
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#define MCP2515_ADDR_CNF3 0x28
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#define MCP2515_ADDR_CNF2 0x29
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#define MCP2515_ADDR_CNF1 0x2A
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#define MCP2515_ADDR_CANINTE 0x2B
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#define MCP2515_ADDR_CANINTF 0x2C
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#define MCP2515_ADDR_EFLG 0x2D
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#define MCP2515_ADDR_TXB0CTRL 0x30
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#define MCP2515_ADDR_TXB1CTRL 0x40
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#define MCP2515_ADDR_TXB2CTRL 0x50
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#define MCP2515_ADDR_RXB0CTRL 0x60
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#define MCP2515_ADDR_RXB1CTRL 0x70
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#define MCP2515_ADDR_OFFSET_FRAME2FRAME 0x10
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#define MCP2515_ADDR_OFFSET_CTRL2FRAME 0x01
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/* MCP2515 Operation Modes */
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#define MCP2515_MODE_NORMAL 0x00
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#define MCP2515_MODE_LOOPBACK 0x02
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#define MCP2515_MODE_SILENT 0x03
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#define MCP2515_MODE_CONFIGURATION 0x04
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/* MCP2515_FRAME_OFFSET */
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#define MCP2515_FRAME_OFFSET_SIDH 0
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#define MCP2515_FRAME_OFFSET_SIDL 1
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#define MCP2515_FRAME_OFFSET_EID8 2
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#define MCP2515_FRAME_OFFSET_EID0 3
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#define MCP2515_FRAME_OFFSET_DLC 4
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#define MCP2515_FRAME_OFFSET_D0 5
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/* MCP2515_CANINTF */
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#define MCP2515_CANINTF_RX0IF BIT(0)
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#define MCP2515_CANINTF_RX1IF BIT(1)
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#define MCP2515_CANINTF_TX0IF BIT(2)
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#define MCP2515_CANINTF_TX1IF BIT(3)
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#define MCP2515_CANINTF_TX2IF BIT(4)
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#define MCP2515_CANINTF_ERRIF BIT(5)
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#define MCP2515_CANINTF_WAKIF BIT(6)
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#define MCP2515_CANINTF_MERRF BIT(7)
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#define MCP2515_INTE_RX0IE BIT(0)
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#define MCP2515_INTE_RX1IE BIT(1)
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#define MCP2515_INTE_TX0IE BIT(2)
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#define MCP2515_INTE_TX1IE BIT(3)
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#define MCP2515_INTE_TX2IE BIT(4)
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#define MCP2515_INTE_ERRIE BIT(5)
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#define MCP2515_INTE_WAKIE BIT(6)
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#define MCP2515_INTE_MERRE BIT(7)
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#define MCP2515_EFLG_EWARN BIT(0)
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#define MCP2515_EFLG_RXWAR BIT(1)
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#define MCP2515_EFLG_TXWAR BIT(2)
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#define MCP2515_EFLG_RXEP BIT(3)
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#define MCP2515_EFLG_TXEP BIT(4)
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#define MCP2515_EFLG_TXBO BIT(5)
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#define MCP2515_EFLG_RX0OVR BIT(6)
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#define MCP2515_EFLG_RX1OVR BIT(7)
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#define MCP2515_TXCTRL_TXREQ BIT(3)
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#define MCP2515_CANSTAT_MODE_POS 5
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#define MCP2515_CANSTAT_MODE_MASK (0x07 << MCP2515_CANSTAT_MODE_POS)
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#define MCP2515_CANCTRL_MODE_POS 5
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#define MCP2515_CANCTRL_MODE_MASK (0x07 << MCP2515_CANCTRL_MODE_POS)
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#endif /*_MCP2515_H_*/
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