156 lines
3.9 KiB
Plaintext
156 lines
3.9 KiB
Plaintext
# STM32 HAL Ethernet driver configuration options
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# Copyright (c) 2017 Erwin Rol <erwin@erwinrol.com>
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# Copyright (c) 2020 Alexander Kozhinov <AlexanderKozhinov@yandex.com>
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# SPDX-License-Identifier: Apache-2.0
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DT_COMPAT_ST_STM32_ETHERNET := st,stm32-ethernet
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menuconfig ETH_STM32_HAL
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bool "STM32 HAL Ethernet driver"
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default y if $(dt_compat_enabled,$(DT_COMPAT_ST_STM32_ETHERNET))
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select USE_STM32_HAL_ETH
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select NOCACHE_MEMORY if SOC_SERIES_STM32H7X && CPU_CORTEX_M7
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help
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Enable STM32 HAL based Ethernet driver. It is available for
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all Ethernet enabled variants of the F2, F4, F7 and H7 series.
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if ETH_STM32_HAL
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config ETH_STM32_HAL_RX_THREAD_STACK_SIZE
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int "RX thread stack size"
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default 1500
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help
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RX thread stack size
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config ETH_STM32_HAL_RX_THREAD_PRIO
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int "RX thread priority"
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default 2
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help
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RX thread priority
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config ETH_STM32_HAL_USE_DTCM_FOR_DMA_BUFFER
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bool "Use DTCM for DMA buffers"
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default y
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depends on SOC_SERIES_STM32F7X
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help
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When this option is activated, the buffers for DMA transfer are
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moved from SRAM to the DTCM (Data Tightly Coupled Memory).
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config ETH_STM32_HAL_PHY_ADDRESS
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int "Phy address"
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default 0
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help
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The phy address to use.
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config ETH_STM32_HAL_RANDOM_MAC
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bool "Random MAC address"
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depends on ENTROPY_GENERATOR
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default y
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help
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Generate a random MAC address dynamically.
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if !ETH_STM32_HAL_RANDOM_MAC
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config ETH_STM32_HAL_MAC3
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hex "MAC Address Byte 3"
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default 0
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range 0 0xff
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help
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This is the byte 3 of the MAC address.
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config ETH_STM32_HAL_MAC4
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hex "MAC Address Byte 4"
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default 0
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range 0 0xff
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help
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This is the byte 4 of the MAC address.
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config ETH_STM32_HAL_MAC5
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hex "MAC Address Byte 5"
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default 0
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range 0 0xff
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help
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This is the byte 5 of the MAC address.
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endif # !ETH_STM32_HAL_RANDOM_MAC
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config ETH_STM32_HAL_MII
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bool "Use MII interface"
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help
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Use the MII physical interface instead of RMII.
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config ETH_STM32_CARRIER_CHECK_RX_IDLE_TIMEOUT_MS
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int "Carrier check timeout period (ms)"
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default 500
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range 100 30000
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help
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Set the RX idle timeout period in milliseconds after which the
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PHY's carrier status is re-evaluated.
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config ETH_STM32_AUTO_NEGOTIATION_ENABLE
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bool "Autonegotiation mode"
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default y
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help
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Enable this if using autonegotiation
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if !ETH_STM32_AUTO_NEGOTIATION_ENABLE
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config ETH_STM32_SPEED_10M
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bool "Set speed to 10 Mbps when autonegotiation is disabled"
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help
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Set this if using 10 Mbps and when autonegotiation is disabled, otherwise speed
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is 100 Mbps
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config ETH_STM32_MODE_HALFDUPLEX
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bool "Half duplex mode"
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help
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Set this if using half duplex when autonegotiation is disabled otherwise
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duplex mode is full duplex
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endif # !ETH_STM32_AUTO_NEGOTIATION_ENABLE
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if SOC_SERIES_STM32F7X || SOC_SERIES_STM32H7X
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config PTP_CLOCK_STM32_HAL
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bool "STM32 HAL PTP clock driver support"
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default y
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depends on PTP_CLOCK || NET_L2_PTP
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help
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Enable STM32 PTP clock support.
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config ETH_STM32_HAL_PTP_CLOCK_SRC_HZ
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int "Frequency of the clock source for the PTP timer"
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default 50000000
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depends on PTP_CLOCK_STM32_HAL
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help
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Set the frequency in Hz sourced to the PTP timer.
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If the value is set properly, the timer will be accurate.
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config ETH_STM32_HAL_PTP_CLOCK_ADJ_MIN_PCT
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int "Lower bound of clock frequency adjustment (in percent)"
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default 90
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depends on PTP_CLOCK_STM32_HAL
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help
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Specifies lower bound of PTP clock rate adjustment.
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config ETH_STM32_HAL_PTP_CLOCK_ADJ_MAX_PCT
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int "Upper bound of clock frequency adjustment (in percent)"
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default 110
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depends on PTP_CLOCK_STM32_HAL
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help
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Specifies upper bound of PTP clock rate adjustment.
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config ETH_STM32_HAL_PTP_CLOCK_INIT_PRIO
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int
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default 85
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depends on PTP_CLOCK_STM32_HAL
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help
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STM32 PTP Clock initialization priority level. There is
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a dependency from the network stack that this device
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initializes before network stack (NET_INIT_PRIO).
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endif # SOC_SERIES_STM32F7X || SOC_SERIES_STM32H7X
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endif # ETH_STM32_HAL
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