zephyr/soc/riscv
Tim Lin 309992280c soc: riscv: enable COMPRESSED_ISA for ITE chips
Enable the config of COMPRESSED_ISA, this can work fine on
32-bit architecture.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-03-25 07:07:19 -04:00
..
litex-vexriscv
openisa_rv32m1
riscv-ite soc: riscv: enable COMPRESSED_ISA for ITE chips 2021-03-25 07:07:19 -04:00
riscv-privilege pinmux: sifive: Convert SiFive pinmux to be devicetree based 2021-02-15 08:33:00 -05:00
CMakeLists.txt