30 lines
699 B
C
30 lines
699 B
C
/*
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* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file SoC configuration macros for the riscv-qemu
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*/
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#ifndef __RISCV32_QEMU_SOC_H_
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#define __RISCV32_QEMU_SOC_H_
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#include <soc_common.h>
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#include <misc/util.h>
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/* UART configuration */
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#define RISCV_QEMU_UART_BASE 0x40002000
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/* Timer configuration */
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#define RISCV_MTIME_BASE 0x40000000
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#define RISCV_MTIMECMP_BASE 0x40000008
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/* lib-c hooks required RAM defined variables */
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#define RISCV_RAM_BASE CONFIG_RISCV_RAM_BASE_ADDR
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#define RISCV_RAM_SIZE MB(CONFIG_RISCV_RAM_SIZE_MB)
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#endif /* __RISCV32_QEMU_SOC_H_ */
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