436 lines
12 KiB
C
436 lines
12 KiB
C
/*
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* Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_ra_gpio
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#include <errno.h>
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#include <string.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/irq.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/drivers/gpio/gpio_utils.h>
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#include <zephyr/drivers/interrupt_controller/intc_ra_icu.h>
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#include <zephyr/drivers/pinctrl.h>
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enum {
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PCNTR1_OFFSET = 0x0,
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PCNTR2_OFFSET = 0x4,
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PCNTR3_OFFSET = 0x8,
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PCNTR4_OFFSET = 0xc
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};
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enum {
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PCNTR1_PDR0_OFFSET = 0,
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PCNTR1_PODR0_OFFSET = 16,
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};
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enum {
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PCNTR2_PIDR0_OFFSET = 0,
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PCNTR2_EIDR0_OFFSET = 16,
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};
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enum {
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PCNTR3_POSR0_OFFSET = 0,
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PCNTR3_PORR0_OFFSET = 16,
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};
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enum {
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PCNTR4_EOSR0_OFFSET = 0,
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PCNTR4_EORR0_OFFSET = 16,
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};
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struct gpio_ra_irq_info {
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const uint8_t *const pins;
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size_t num;
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int port_irq;
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int irq;
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uint32_t priority;
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uint32_t flags;
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ra_isr_handler isr;
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};
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struct gpio_ra_pin_irq_info {
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const struct gpio_ra_irq_info *info;
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uint8_t pin;
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};
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struct gpio_ra_config {
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struct gpio_driver_config common;
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mem_addr_t regs;
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struct gpio_ra_irq_info *irq_info;
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uint32_t irq_info_size;
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uint16_t port;
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};
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struct gpio_ra_data {
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struct gpio_driver_data common;
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struct gpio_ra_pin_irq_info port_irq_info[16];
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sys_slist_t callbacks;
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};
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static inline uint32_t gpio_ra_irq_info_event(const struct gpio_ra_irq_info *info)
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{
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return ((info->flags & RA_ICU_FLAG_EVENT_MASK) >> RA_ICU_FLAG_EVENT_OFFSET);
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}
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static void gpio_ra_isr(const struct device *dev, uint32_t port_irq)
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{
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struct gpio_ra_data *data = dev->data;
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const struct gpio_ra_pin_irq_info *pin_irq = &data->port_irq_info[port_irq];
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const int irq = ra_icu_query_exists_irq(gpio_ra_irq_info_event(pin_irq->info));
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if (irq >= 0) {
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gpio_fire_callbacks(&data->callbacks, dev, BIT(pin_irq->pin));
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ra_icu_clear_int_flag(irq);
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}
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}
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static const struct gpio_ra_irq_info *query_irq_info(const struct device *dev, uint32_t pin)
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{
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const struct gpio_ra_config *config = dev->config;
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for (int i = 0; i < config->irq_info_size; i++) {
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const struct gpio_ra_irq_info *info = &config->irq_info[i];
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for (int j = 0; j < info->num; j++) {
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if (info->pins[j] == pin) {
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return info;
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}
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}
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}
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return NULL;
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}
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static inline uint32_t reg_read(const struct device *dev, size_t offset)
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{
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const struct gpio_ra_config *config = dev->config;
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return sys_read32(config->regs + offset);
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}
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static inline void reg_write(const struct device *dev, size_t offset, uint32_t value)
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{
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const struct gpio_ra_config *config = dev->config;
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sys_write32(value, config->regs + offset);
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}
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static inline uint32_t port_read(const struct device *dev)
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{
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return reg_read(dev, PCNTR2_OFFSET) & UINT16_MAX;
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}
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static int port_write(const struct device *dev, uint16_t value, uint16_t mask)
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{
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const uint16_t set = value & mask;
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const uint16_t clr = (~value) & mask;
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reg_write(dev, PCNTR3_OFFSET, (clr << PCNTR3_PORR0_OFFSET) | set << PCNTR3_POSR0_OFFSET);
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return 0;
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}
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static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
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{
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const enum gpio_int_mode mode =
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flags & (GPIO_INT_EDGE | GPIO_INT_DISABLE | GPIO_INT_ENABLE);
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const enum gpio_int_trig trig = flags & (GPIO_INT_LOW_0 | GPIO_INT_HIGH_1);
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const struct gpio_ra_config *config = dev->config;
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struct gpio_ra_data *data = dev->data;
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struct pinctrl_ra_pin pincfg = {0};
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if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) {
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/* Pin cannot be configured as input and output */
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return -ENOTSUP;
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} else if (!(flags & (GPIO_INPUT | GPIO_OUTPUT))) {
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/* Pin has to be configured as input or output */
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return -ENOTSUP;
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}
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if (flags & GPIO_OUTPUT) {
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pincfg.config |= BIT(PmnPFS_PDR_POS);
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}
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if (flags & GPIO_PULL_UP) {
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pincfg.config |= BIT(PmnPFS_PCR_POS);
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}
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if ((flags & GPIO_SINGLE_ENDED) && (flags & GPIO_LINE_OPEN_DRAIN)) {
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pincfg.config |= BIT(PmnPFS_NCODR_POS);
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}
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if (flags & GPIO_INT_ENABLE) {
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pincfg.config |= BIT(PmnPFS_ISEL_POS);
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}
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pincfg.config &= ~BIT(PmnPFS_PMR_POS);
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pincfg.pin = pin;
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pincfg.port = config->port;
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if (flags & GPIO_INT_ENABLE) {
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const struct gpio_ra_irq_info *irq_info;
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uint32_t intcfg;
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int irqn;
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if (mode == GPIO_INT_MODE_LEVEL) {
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if (trig != GPIO_INT_TRIG_LOW) {
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return -ENOTSUP;
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}
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intcfg = ICU_LOW_LEVEL;
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} else if (mode == GPIO_INT_MODE_EDGE) {
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switch (trig) {
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case GPIO_INT_TRIG_LOW:
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intcfg = ICU_FALLING;
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break;
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case GPIO_INT_TRIG_HIGH:
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intcfg = ICU_RISING;
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break;
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case GPIO_INT_TRIG_BOTH:
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intcfg = ICU_BOTH_EDGE;
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break;
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default:
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return -ENOTSUP;
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}
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} else {
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return -ENOTSUP;
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}
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irq_info = query_irq_info(dev, pin);
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if (irq_info == NULL) {
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return -EINVAL;
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}
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irqn = ra_icu_irq_connect_dynamic(
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irq_info->irq, irq_info->priority, irq_info->isr, dev,
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(intcfg << RA_ICU_FLAG_INTCFG_OFFSET) | irq_info->flags);
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if (irqn < 0) {
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return irqn;
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}
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data->port_irq_info[irq_info->port_irq].pin = pin;
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data->port_irq_info[irq_info->port_irq].info = irq_info;
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irq_enable(irqn);
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}
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return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE);
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}
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#ifdef CONFIG_GPIO_GET_CONFIG
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static int gpio_ra_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags)
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{
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const struct gpio_ra_config *config = dev->config;
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const struct gpio_ra_irq_info *irq_info;
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struct pinctrl_ra_pin pincfg;
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ra_isr_handler cb;
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const void *cbarg;
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uint32_t intcfg;
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int irqn;
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int err;
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memset(flags, 0, sizeof(gpio_flags_t));
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err = pinctrl_ra_query_config(config->port, pin, &pincfg);
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if (err < 0) {
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return err;
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}
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if (pincfg.config & BIT(PmnPFS_PDR_POS)) {
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*flags |= GPIO_OUTPUT;
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} else {
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*flags |= GPIO_INPUT;
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}
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if (pincfg.config & BIT(PmnPFS_ISEL_POS)) {
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*flags |= GPIO_INT_ENABLE;
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}
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if (pincfg.config & BIT(PmnPFS_PCR_POS)) {
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*flags |= GPIO_PULL_UP;
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}
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irq_info = query_irq_info(dev, pin);
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if (irq_info == NULL) {
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return 0;
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}
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irqn = ra_icu_query_exists_irq(gpio_ra_irq_info_event(irq_info));
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if (irqn < 0) {
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return 0;
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}
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ra_icu_query_irq_config(irqn, &intcfg, &cb, &cbarg);
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if (cbarg != dev) {
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return 0;
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}
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if (intcfg == ICU_FALLING) {
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*flags |= GPIO_INT_TRIG_LOW;
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*flags |= GPIO_INT_MODE_EDGE;
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} else if (intcfg == ICU_RISING) {
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*flags |= GPIO_INT_TRIG_HIGH;
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*flags |= GPIO_INT_MODE_EDGE;
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} else if (intcfg == ICU_BOTH_EDGE) {
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*flags |= GPIO_INT_TRIG_BOTH;
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*flags |= GPIO_INT_MODE_EDGE;
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} else if (intcfg == ICU_LOW_LEVEL) {
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*flags |= GPIO_INT_TRIG_LOW;
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*flags |= GPIO_INT_MODE_LEVEL;
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}
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return 0;
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}
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#endif
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static int gpio_ra_port_get_raw(const struct device *dev, gpio_port_value_t *value)
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{
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*value = port_read(dev);
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return 0;
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}
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static int gpio_ra_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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uint16_t port_val;
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port_val = port_read(dev);
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port_val = (port_val & ~mask) | (value & mask);
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return port_write(dev, port_val, UINT16_MAX);
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}
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static int gpio_ra_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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uint16_t port_val;
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port_val = port_read(dev);
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port_val |= pins;
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return port_write(dev, port_val, UINT16_MAX);
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}
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static int gpio_ra_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
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{
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uint16_t port_val;
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port_val = port_read(dev);
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port_val &= ~pins;
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return port_write(dev, port_val, UINT16_MAX);
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}
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static int gpio_ra_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
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{
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uint16_t port_val;
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port_val = port_read(dev);
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port_val ^= pins;
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return port_write(dev, port_val, UINT16_MAX);
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}
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static int gpio_ra_manage_callback(const struct device *dev, struct gpio_callback *callback,
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bool set)
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{
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struct gpio_ra_data *data = dev->data;
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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static int gpio_ra_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
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enum gpio_int_mode mode, enum gpio_int_trig trig)
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{
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gpio_flags_t pincfg;
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int err;
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err = gpio_ra_pin_get_config(dev, pin, &pincfg);
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if (err < 0) {
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return err;
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}
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return gpio_ra_pin_configure(dev, pin, pincfg | mode | trig);
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}
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static const struct gpio_driver_api gpio_ra_driver_api = {
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.pin_configure = gpio_ra_pin_configure,
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#ifdef CONFIG_GPIO_GET_CONFIG
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.pin_get_config = gpio_ra_pin_get_config,
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#endif
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.port_get_raw = gpio_ra_port_get_raw,
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.port_set_masked_raw = gpio_ra_port_set_masked_raw,
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.port_set_bits_raw = gpio_ra_port_set_bits_raw,
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.port_clear_bits_raw = gpio_ra_port_clear_bits_raw,
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.port_toggle_bits = gpio_ra_port_toggle_bits,
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.pin_interrupt_configure = gpio_ra_pin_interrupt_configure,
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.manage_callback = gpio_ra_manage_callback,
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};
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#define RA_NUM_PORT_IRQ0 0
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#define RA_NUM_PORT_IRQ1 1
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#define RA_NUM_PORT_IRQ2 2
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#define RA_NUM_PORT_IRQ3 3
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#define RA_NUM_PORT_IRQ4 4
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#define RA_NUM_PORT_IRQ5 5
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#define RA_NUM_PORT_IRQ6 6
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#define RA_NUM_PORT_IRQ7 7
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#define RA_NUM_PORT_IRQ8 8
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#define RA_NUM_PORT_IRQ9 9
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#define RA_NUM_PORT_IRQ10 10
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#define RA_NUM_PORT_IRQ11 11
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#define RA_NUM_PORT_IRQ12 12
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#define RA_NUM_PORT_IRQ13 13
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#define RA_NUM_PORT_IRQ14 14
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#define RA_NUM_PORT_IRQ15 15
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#define GPIO_RA_DECL_PINS(n, p, i) \
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const uint8_t _CONCAT(n, ___pins##i[]) = {DT_FOREACH_PROP_ELEM_SEP( \
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n, _CONCAT(DT_STRING_TOKEN_BY_IDX(n, p, i), _pins), DT_PROP_BY_IDX, (,))};
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#define GPIO_RA_IRQ_INFO(n, p, i) \
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{ \
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.port_irq = _CONCAT(RA_NUM_, DT_STRING_UPPER_TOKEN_BY_IDX(n, p, i)), \
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.irq = DT_IRQ_BY_IDX(n, i, irq), \
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.flags = DT_IRQ_BY_IDX(n, i, flags), \
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.priority = DT_IRQ_BY_IDX(n, i, priority), \
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.pins = _CONCAT(n, ___pins##i), \
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.num = ARRAY_SIZE(_CONCAT(n, ___pins##i)), \
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.isr = _CONCAT(n, _CONCAT(gpio_ra_isr_, DT_STRING_TOKEN_BY_IDX(n, p, i))), \
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},
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#define GPIO_RA_ISR_DECL(n, p, i) \
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static void _CONCAT(n, _CONCAT(gpio_ra_isr_, DT_STRING_TOKEN_BY_IDX(n, p, i)))( \
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const void *arg) \
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{ \
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gpio_ra_isr((const struct device *)arg, \
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_CONCAT(RA_NUM_, DT_STRING_UPPER_TOKEN_BY_IDX(n, p, i))); \
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}
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#define GPIO_RA_INIT(idx) \
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static struct gpio_ra_data gpio_ra_data_##idx = {}; \
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DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, GPIO_RA_DECL_PINS); \
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DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, GPIO_RA_ISR_DECL); \
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struct gpio_ra_irq_info gpio_ra_irq_info_##idx[] = { \
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DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, GPIO_RA_IRQ_INFO)}; \
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static struct gpio_ra_config gpio_ra_config_##idx = { \
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.common = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx), \
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}, \
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.regs = DT_INST_REG_ADDR(idx), \
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.port = (DT_INST_REG_ADDR(idx) - DT_REG_ADDR(DT_NODELABEL(ioport0))) / \
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DT_INST_REG_SIZE(idx), \
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.irq_info = gpio_ra_irq_info_##idx, \
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.irq_info_size = ARRAY_SIZE(gpio_ra_irq_info_##idx), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(idx, NULL, NULL, &gpio_ra_data_##idx, &gpio_ra_config_##idx, \
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PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_ra_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(GPIO_RA_INIT)
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