154 lines
3.4 KiB
C
154 lines
3.4 KiB
C
/*
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* Copyright (c) 2021 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <string.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/fpga.h>
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#include "fpga_eos_s3.h"
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void eos_s3_fpga_enable_clk(void)
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{
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CRU->C16_CLK_GATE = C16_CLK_GATE_PATH_0_ON;
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CRU->C21_CLK_GATE = C21_CLK_GATE_PATH_0_ON;
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CRU->C09_CLK_GATE = C09_CLK_GATE_PATH_1_ON | C09_CLK_GATE_PATH_2_ON;
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CRU->C02_CLK_GATE = C02_CLK_GATE_PATH_1_ON;
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}
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void eos_s3_fpga_disable_clk(void)
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{
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CRU->C16_CLK_GATE = C16_CLK_GATE_PATH_0_OFF;
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CRU->C21_CLK_GATE = C21_CLK_GATE_PATH_0_OFF;
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CRU->C09_CLK_GATE = C09_CLK_GATE_PATH_1_OFF | C09_CLK_GATE_PATH_2_OFF;
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CRU->C02_CLK_GATE = C02_CLK_GATE_PATH_1_OFF;
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}
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struct quickfeather_fpga_data {
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char *FPGA_info;
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};
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static enum FPGA_status eos_s3_fpga_get_status(const struct device *dev)
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{
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ARG_UNUSED(dev);
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if (PMU->FB_STATUS == FPGA_STATUS_ACTIVE) {
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return FPGA_STATUS_ACTIVE;
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} else {
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return FPGA_STATUS_INACTIVE;
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}
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}
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static const char *eos_s3_fpga_get_info(const struct device *dev)
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{
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struct quickfeather_fpga_data *data = dev->data;
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return data->FPGA_info;
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}
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static int eos_s3_fpga_on(const struct device *dev)
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{
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if (eos_s3_fpga_get_status(dev) == FPGA_STATUS_ACTIVE) {
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return 0;
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}
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/* wake up the FPGA power domain */
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PMU->FFE_FB_PF_SW_WU = PMU_FFE_FB_PF_SW_WU_FB_WU;
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while (PMU->FFE_FB_PF_SW_WU == PMU_FFE_FB_PF_SW_WU_FB_WU) {
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/* The register will clear itself if the FPGA starts */
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};
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eos_s3_fpga_enable_clk();
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/* enable FPGA programming */
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PMU->GEN_PURPOSE_0 = FB_CFG_ENABLE;
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PIF->CFG_CTL = CFG_CTL_LOAD_ENABLE;
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return 0;
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}
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static int eos_s3_fpga_off(const struct device *dev)
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{
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if (eos_s3_fpga_get_status(dev) == FPGA_STATUS_INACTIVE) {
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return 0;
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}
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PMU->FB_PWR_MODE_CFG = PMU_FB_PWR_MODE_CFG_FB_SD;
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PMU->FFE_FB_PF_SW_PD = PMU_FFE_FB_PF_SW_PD_FB_PD;
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eos_s3_fpga_disable_clk();
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return 0;
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}
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static int eos_s3_fpga_reset(const struct device *dev)
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{
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if (eos_s3_fpga_get_status(dev) == FPGA_STATUS_ACTIVE) {
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eos_s3_fpga_off(dev);
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}
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eos_s3_fpga_on(dev);
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if (eos_s3_fpga_get_status(dev) == FPGA_STATUS_INACTIVE) {
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return -EAGAIN;
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}
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return 0;
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}
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static int eos_s3_fpga_load(const struct device *dev, uint32_t *image_ptr, uint32_t img_size)
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{
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if (eos_s3_fpga_get_status(dev) == FPGA_STATUS_INACTIVE) {
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return -EINVAL;
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}
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volatile uint32_t *bitstream = (volatile uint32_t *)image_ptr;
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for (uint32_t chunk_cnt = 0; chunk_cnt < (img_size / 4); chunk_cnt++) {
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PIF->CFG_DATA = *bitstream;
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bitstream++;
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}
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/* disable FPGA programming */
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PMU->GEN_PURPOSE_0 = FB_CFG_DISABLE;
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PIF->CFG_CTL = CFG_CTL_LOAD_DISABLE;
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PMU->FB_ISOLATION = FB_ISOLATION_DISABLE;
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/* disable software resets */
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CRU->FB_SW_RESET &= ~(FB_C21_DOMAIN_SW_RESET
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| FB_C16_DOMAIN_SW_RESET
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| FB_C02_DOMAIN_SW_RESET
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| FB_C09_DOMAIN_SW_RESET);
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return 0;
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}
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static int eos_s3_fpga_init(const struct device *dev)
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{
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IO_MUX->PAD_19_CTRL = PAD_ENABLE;
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struct quickfeather_fpga_data *data = dev->data;
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data->FPGA_info = FPGA_INFO;
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eos_s3_fpga_reset(dev);
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return 0;
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}
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static struct quickfeather_fpga_data fpga_data;
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static const struct fpga_driver_api eos_s3_api = {
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.reset = eos_s3_fpga_reset,
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.load = eos_s3_fpga_load,
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.get_status = eos_s3_fpga_get_status,
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.on = eos_s3_fpga_on,
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.off = eos_s3_fpga_off,
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.get_info = eos_s3_fpga_get_info
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(fpga0), &eos_s3_fpga_init, NULL, &fpga_data, NULL, POST_KERNEL,
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CONFIG_FPGA_INIT_PRIORITY, &eos_s3_api);
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