104 lines
2.4 KiB
C
104 lines
2.4 KiB
C
/*
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* Copyright (c) 2024 GARDENA GmbH
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT silabs_si32_ahb
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#include <stdint.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/clock_control.h>
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#include <SI32_CLKCTRL_A_Type.h>
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#include <SI32_FLASHCTRL_A_Type.h>
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#include <si32_device.h>
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#define LOG_LEVEL LOG_LEVEL_DBG
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(ahb);
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struct clock_control_si32_ahb_config {
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const struct device *clock_dev;
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uint32_t freq;
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};
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static int clock_control_si32_ahb_on(const struct device *dev, clock_control_subsys_t sys)
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{
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return -ENOTSUP;
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}
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static int clock_control_si32_ahb_off(const struct device *dev, clock_control_subsys_t sys)
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{
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return -ENOTSUP;
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}
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static int clock_control_si32_ahb_get_rate(const struct device *dev, clock_control_subsys_t sys,
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uint32_t *rate)
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{
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const struct clock_control_si32_ahb_config *config = dev->config;
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*rate = config->freq;
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return 0;
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}
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static struct clock_control_driver_api clock_control_si32_ahb_api = {
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.on = clock_control_si32_ahb_on,
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.off = clock_control_si32_ahb_off,
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.get_rate = clock_control_si32_ahb_get_rate,
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};
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static int clock_control_si32_ahb_init(const struct device *dev)
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{
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const struct clock_control_si32_ahb_config *config = dev->config;
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int ret;
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if (!device_is_ready(config->clock_dev)) {
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return -ENODEV;
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}
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if (config->freq != 20000000) {
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uint32_t freq = config->freq;
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ret = clock_control_set_rate(config->clock_dev, NULL, &freq);
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if (ret) {
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LOG_ERR("failed to set parent clock rate: %d", ret);
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return ret;
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}
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ret = clock_control_on(config->clock_dev, NULL);
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if (ret) {
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LOG_ERR("failed to enable parent clock: %d", ret);
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return ret;
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}
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uint32_t spmd;
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if (config->freq > 80000000) {
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spmd = 3;
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} else if (config->freq > 53000000) {
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spmd = 2;
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} else if (config->freq > 26000000) {
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spmd = 1;
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} else {
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spmd = 0;
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}
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SI32_FLASHCTRL_A_select_flash_speed_mode(SI32_FLASHCTRL_0, spmd);
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/* TODO: support other clock sources */
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SI32_CLKCTRL_A_select_ahb_source_pll(SI32_CLKCTRL_0);
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}
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return 0;
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}
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static const struct clock_control_si32_ahb_config config = {
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
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.freq = DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency),
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};
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DEVICE_DT_INST_DEFINE(0, clock_control_si32_ahb_init, NULL, NULL, &config, PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_control_si32_ahb_api);
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