41 lines
1.1 KiB
C
41 lines
1.1 KiB
C
/*
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* Copyright (c) 2021 Katsuhiro Suzuki
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/sys/util.h>
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#include "prci.h"
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BUILD_ASSERT(MHZ(1000) == DT_PROP(DT_NODELABEL(coreclk), clock_frequency),
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"Unsupported CORECLK frequency");
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BUILD_ASSERT(DT_PROP(DT_NODELABEL(tlclk), clock_div) == 2,
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"Unsupported TLCLK divider");
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/*
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* Switch the clock source to 1GHz PLL from 33.333MHz oscillator on the HiFive
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* Unleashed board.
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*/
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static int fu540_clock_init(void)
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{
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PRCI_REG(PRCI_COREPLLCFG0) =
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PLL_R(0) | /* input divider: Fin / (0 + 1) = 33.33MHz */
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PLL_F(59) | /* VCO: 2 x (59 + 1) = 120 = 3999.6MHz */
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PLL_Q(2) | /* output divider: VCO / 2^2 = 999.9MHz */
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PLL_RANGE(PLL_RANGE_33MHZ) |
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PLL_BYPASS(PLL_BYPASS_DISABLE) |
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PLL_FSE(PLL_FSE_INTERNAL);
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while ((PRCI_REG(PRCI_COREPLLCFG0) & PLL_LOCK(1)) == 0)
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;
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/* Switch clock to COREPLL */
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PRCI_REG(PRCI_CORECLKSEL) = CORECLKSEL_CORECLKSEL(CORECLKSEL_CORE_PLL);
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return 0;
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}
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SYS_INIT(fu540_clock_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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