81 lines
1.6 KiB
C
81 lines
1.6 KiB
C
/*
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* Copyright (c) 2020 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/arm/arch.h>
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#include <zephyr/kernel.h>
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#include <zephyr/sys_clock.h>
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#include <zephyr/timing/timing.h>
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#include <nrfx.h>
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#if defined(CONFIG_NRF_RTC_TIMER)
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#define CYCLES_PER_SEC (16000000 / (1 << NRF_TIMER2->PRESCALER))
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void soc_timing_init(void)
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{
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NRF_TIMER2->TASKS_CLEAR = 1; /* Clear Timer */
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NRF_TIMER2->MODE = 0; /* Timer Mode */
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NRF_TIMER2->PRESCALER = 0; /* 16M Hz */
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#if defined(CONFIG_SOC_SERIES_NRF51X)
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NRF_TIMER2->BITMODE = 0; /* 16 - bit */
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#else
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NRF_TIMER2->BITMODE = 3; /* 32 - bit */
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#endif
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}
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void soc_timing_start(void)
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{
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NRF_TIMER2->TASKS_START = 1;
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}
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void soc_timing_stop(void)
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{
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NRF_TIMER2->TASKS_STOP = 1; /* Stop Timer */
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}
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timing_t soc_timing_counter_get(void)
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{
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NRF_TIMER2->TASKS_CAPTURE[0] = 1;
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return NRF_TIMER2->CC[0] * ((SystemCoreClock) / CYCLES_PER_SEC);
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}
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uint64_t soc_timing_cycles_get(volatile timing_t *const start,
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volatile timing_t *const end)
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{
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#if defined(CONFIG_SOC_SERIES_NRF51X)
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#define COUNTER_SPAN BIT(16)
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if (*end >= *start) {
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return (*end - *start);
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} else {
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return COUNTER_SPAN + *end - *start;
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}
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#else
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return (*end - *start);
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#endif
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}
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uint64_t soc_timing_freq_get(void)
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{
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return SystemCoreClock;
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}
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uint64_t soc_timing_cycles_to_ns(uint64_t cycles)
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{
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return (cycles) * (NSEC_PER_SEC) / (SystemCoreClock);
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}
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uint64_t soc_timing_cycles_to_ns_avg(uint64_t cycles, uint32_t count)
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{
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return soc_timing_cycles_to_ns(cycles) / count;
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}
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uint32_t soc_timing_freq_get_mhz(void)
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{
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return (uint32_t)(soc_timing_freq_get() / 1000000);
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}
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#endif
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