81 lines
1.7 KiB
Plaintext
81 lines
1.7 KiB
Plaintext
/*
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* Copyright (c) 2021 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa/xtensa.dtsi>
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#include <mem.h>
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#include <zephyr/dt-bindings/clock/imx_ccm.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx6";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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clic: interrupt-controller@0 {
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compatible = "cdns,xtensa-core-intc";
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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};
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};
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sram0: memory@92400000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x92400000 DT_SIZE_K(512)>;
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};
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sram1: memory@92c00000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0x92c00000 DT_SIZE_K(512)>;
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};
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/* LSIO MU2, used to interact with the SCFW */
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scu_mu: mailbox@5d1d0000 {
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reg = <0x5d1d0000 DT_SIZE_K(64)>;
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};
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scu: system-controller {
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ccm: clock-controller {
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compatible = "nxp,imx-ccm";
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#clock-cells = <3>;
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};
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iomuxc: iomuxc {
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compatible = "nxp,imx-iomuxc-scu";
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pinctrl: pinctrl {
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compatible = "nxp,imx8-pinctrl";
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};
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};
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};
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lpuart2: serial@5a080000 {
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compatible = "nxp,imx-lpuart", "nxp,kinetis-lpuart";
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reg = <0x5a080000 DT_SIZE_K(4)>;
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/* TODO: THIS INTID IS JUST A DUMMY ONE UNTIL IRQ_STEER
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* DRIVER CAN BE USED ON i.MX8QM/QXP. DO NOT ATTEMPT TO
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* ENABLE UART INTERRUPT SUPPORT.
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*
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* THE CURRENT INTID VALUE IS CHOSEN SUCH THAT gen_isr_tables.py
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* WILL BREAK IF YOU ATTEMPT TO IRQ_CONNECT().
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*/
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interrupt-parent = <&clic>;
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interrupts = <259 0 0>;
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/* this is actually LPUART2 clock but the macro indexing starts at 1 */
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clocks = <&ccm IMX_CCM_LPUART3_CLK 0x0 0x0>;
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status = "disabled";
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};
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};
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