63 lines
1.4 KiB
C
63 lines
1.4 KiB
C
/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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* Copyright (c) 2021 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief Cache manipulation
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*
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* This module contains functions for manipulation caches.
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <sys/util.h>
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#include <toolchain.h>
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#include <cache.h>
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#include <stdbool.h>
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/**
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* @brief Flush cache lines to main memory
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*
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* No alignment is required for either <virt> or <size>, but since
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* sys_cache_flush() iterates on the cache lines, a cache line alignment for
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* both is optimal.
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*
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* The cache line size is specified via the d-cache-line-size DTS property.
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*/
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static void arch_dcache_flush(void *start_addr, size_t size)
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{
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size_t line_size = sys_cache_data_line_size_get();
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uintptr_t start = (uintptr_t)start_addr;
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uintptr_t end = start + size;
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if (line_size == 0U) {
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return;
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}
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end = ROUND_UP(end, line_size);
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for (; start < end; start += line_size) {
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__asm__ volatile("clflush %0;\n\t" :
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"+m"(*(volatile char *)start));
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}
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#if defined(CONFIG_X86_MFENCE_INSTRUCTION_SUPPORTED)
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__asm__ volatile("mfence;\n\t":::"memory");
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#else
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__asm__ volatile("lock; addl $0,-4(%%esp);\n\t":::"memory", "cc");
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#endif
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}
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int arch_dcache_range(void *addr, size_t size, int op)
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{
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if (op & K_CACHE_WB) {
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arch_dcache_flush(addr, size);
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return 0;
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}
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return -ENOTSUP;
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}
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