zephyr/soc/riscv/openisa_rv32m1
Øyvind Rønningstad 05f0d85b6a extensions.cmake: Replace TEXT_START with ROM_START
In zephyr_linker_sources().
This is done since the point of the location is to place things at given
offsets. This can only be done consistenly if the linker code is placed
into the _first_ section.

All uses of TEXT_START are replaced with ROM_START.

ROM_START is only supported in some arches, as some arches have several
custom sections before text. These don't currently have ROM_START or
TEXT_START available, but that could be added with a bit of refactoring
in their linker script.

No SORT_KEYs are changed.

This also fixes an error introduced when TEXT_START was added, where
TEXT_SECTION_OFFSET was applied to riscv's common linker.ld instead of
to openisa_rv32m1's specific linker.ld.

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
2020-01-23 03:22:59 -08:00
..
CMakeLists.txt extensions.cmake: Replace TEXT_START with ROM_START 2020-01-23 03:22:59 -08:00
Kconfig
Kconfig.defconfig soc: riscv: rv32m1: enable the RV32M1 Timer/PWM driver 2020-01-13 09:12:34 -06:00
Kconfig.soc modules: vega: add option for indicating the presence of RV32M1 TPM 2020-01-13 09:12:34 -06:00
dts_fixup.h
linker.ld extensions.cmake: Replace TEXT_START with ROM_START 2020-01-23 03:22:59 -08:00
soc.c soc: riscv: rv32m1: enable peripheral clocks for Timer/PWM modules 2020-01-13 09:12:34 -06:00
soc.h devicetree: Remove DT_SRAM_{BASE_ADDRESS,SIZE}, use CONFIG_* versions 2020-01-07 17:19:36 +01:00
soc_context.h
soc_irq.S
soc_offsets.h
soc_ri5cy.h riscv: use standard MSTATUS 2020-01-06 13:27:45 -05:00
soc_zero_riscy.h riscv: use standard MSTATUS 2020-01-06 13:27:45 -05:00
vector.S
vector_table.ld riscv: linker.ld: Port vector table to zephyr_linker_sources() 2019-12-20 08:54:53 -05:00
wdog.S riscv: use standard MSTATUS 2020-01-06 13:27:45 -05:00