zephyr/arch/xtensa/core
Flavio Ceolin da49f2e440 coccicnelle: Ignore return of memset
The return of memset is never checked. This patch explicitly ignore
the return to avoid MISRA-C violations.

The only directory excluded directory was ext/* since it contains
only imported code.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-14 16:55:37 -04:00
..
offsets kbuild: Removed KBuild 2017-11-08 20:00:22 -05:00
startup arch: xtensa: set __start as entry point for Xtensa. 2018-05-01 16:46:41 -04:00
CMakeLists.txt xtensa/asm2: Don't needlessly build asm2 sources 2018-02-16 10:44:29 -05:00
atomic.S
cpu_idle.c xtensa: removed obsolete headers 2018-09-01 13:58:46 -04:00
crt1.S arch: xtensa: set __start as entry point for Xtensa. 2018-05-01 16:46:41 -04:00
fatal.c esp32: update to ESP-IDF v3.0-dev-2648-gb2ff235b 2018-06-13 18:53:43 -04:00
irq_manage.c arch: convert to using newly introduced integer sized types 2017-04-21 12:08:12 +00:00
irq_offload.c kernel: remove all remaining references to nanokernel 2017-04-10 20:21:10 +00:00
swap.S systemview: add support natively using tracing hooks 2018-08-21 05:45:47 -07:00
thread.c coccicnelle: Ignore return of memset 2018-09-14 16:55:37 -04:00
window_vectors.S xtensa: Move register window exception handlers into a separate file 2018-02-16 10:44:29 -05:00
xt_zephyr.S kernel: Remove legacy preemption checking 2018-05-25 09:40:55 -07:00
xtensa-asm2-util.S tests: benchmarks: timing_info: Enable benchmarks for xtensa. 2018-08-20 06:51:25 -07:00
xtensa-asm2.c coccicnelle: Ignore return of memset 2018-09-14 16:55:37 -04:00
xtensa_context.S
xtensa_intgen.py xtensa: Interrupt generator script and output for qemu & esp32 2018-02-16 10:44:29 -05:00
xtensa_intgen.tmpl xtensa: Interrupt generator script and output for qemu & esp32 2018-02-16 10:44:29 -05:00
xtensa_intr.c xtensa: Remove _xt_set_exception_handler() 2018-02-16 10:44:29 -05:00
xtensa_intr_asm.S arch: xtensa: Move exception table to xtensa_intr.c 2017-08-09 12:26:14 -07:00
xtensa_vectors.S arch: xtensa: remove extra #endif 2018-09-04 14:27:33 -04:00