84 lines
2.3 KiB
Plaintext
84 lines
2.3 KiB
Plaintext
# Kconfig - Atmel SAM4S MCU series
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#
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# Copyright (c) 2017 Justin Watson
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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choice
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prompt "Atmel SAM4S MCU Selection"
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depends on SOC_SERIES_SAM4S
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config SOC_PART_NUMBER_SAM4S16C
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bool "SAM4S16C"
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endchoice
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if SOC_SERIES_SAM4S
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config SOC_ATMEL_SAM4S_EXT_SLCK
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bool "Atmel SAM4S to use external crystal oscillator for slow clock"
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default n
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help
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Says y if you want to use external 32 kHz crystal
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oscillator to drive the slow clock. Note that this
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adds a few seconds to boot time, as the crystal
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needs to stabilize after power-up.
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Says n if you do not need accurate and precise timers.
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The slow clock will be driven by the internal fast
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RC oscillator running at 32 kHz.
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config SOC_ATMEL_SAM4S_EXT_MAINCK
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bool "Atmel SAM4S to use external crystal oscillator for main clock"
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default n
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help
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The main clock is being used to drive the PLL, and
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thus driving the processor clock.
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Says y if you want to use external crystal oscillator
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to drive the main clock. Note that this adds about
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a second to boot time, as the crystal needs to
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stabilize after power-up.
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The crystal used here can be from 3 to 20 MHz.
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Says n here will use the internal fast RC oscillator
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running at 12 MHz.
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config SOC_ATMEL_SAM4S_PLLA_MULA
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hex "PLL MULA"
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default 0x09
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help
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This is the multiplier (MULA) used by the PLL.
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The processor clock is (MAINCK * (MULA + 1) / DIVA).
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Board config file can override this settings
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for a particular board.
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With default of MULA == 9, and DIVA == 1,
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PLL is running at 10 times of main clock.
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config SOC_ATMEL_SAM4S_PLLA_DIVA
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hex "PLL DIVA"
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default 0x01
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help
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This is the divider (DIVA) used by the PLL.
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The processor clock is (MAINCK * (MULA + 1) / DIVA).
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Board config file can override this settings
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for a particular board.
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With default of MULA == 9, and DIVA == 1,
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PLL is running at 10 times of main clock.
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config SOC_ATMEL_SAM4S_WAIT_MODE
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bool "Atmel SAM4S goes to Wait mode instead of Sleep mode"
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depends on SOC_ATMEL_SAM4S_EXT_MAINCK
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default y if DEBUG
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help
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For JTAG debugging CPU clock (HCLK) should not stop. In order
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to achieve this, make CPU go to Wait mode instead of Sleep
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mode while using external crystal oscillator for main clock.
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endif # SOC_SERIES_SAM4S
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