Daniel Leung 8a79ce1428 riscv: add support for thread local storage ... Adds the necessary bits to initialize TLS in the stack area and sets up CPU registers during context switch. Signed-off-by: Daniel Leung <daniel.leung@intel.com>		2020-10-24 10:52:00 -07:00
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CMakeLists.txt	…
Kconfig	…
Kconfig.defconfig	arch: xip: cleanup XIP Kconfig	2020-08-07 09:50:22 -04:00
Kconfig.soc	…
linker.ld	riscv: add support for thread local storage	2020-10-24 10:52:00 -07:00
soc.c	device: Const-ify all device driver instance pointers	2020-09-02 13:48:13 +02:00
soc.h	zephyr: replace zephyr integer types with C99 types	2020-06-08 08:23:57 -05:00
soc_context.h	arch: riscv: thread: Init soc context on stack	2020-07-13 15:00:19 -05:00
soc_irq.S	…
soc_offsets.h	soc: riscv: rv32m1: Fix optional context save	2020-07-13 15:00:19 -05:00
soc_ri5cy.h	…
soc_zero_riscy.h	…
vector.S	…
vector_table.ld	config: Rename TEXT_SECTION_OFFSET to ROM_START_OFFSET	2020-07-09 14:02:38 -04:00
wdog.S	…