Adrian Warecki 1c5f924628 ace: cavs: dts: Add d-cache and i-cache line size ... Added i-cache-line-size and d-cache-line-size values to device tree for cavs and ace platforms. These values are used by sys_cache_instr_line_size_get and sys_cache_data_line_size_get functions. Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>		2022-11-23 15:39:05 -05:00
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arc/synopsys	soc: arc: define ICI in DT	2022-08-03 07:46:14 -04:00
arm	dts: nxp_rt6xx: correct FlexSPI memory mapped region size	2022-11-21 13:03:26 +01:00
arm64	boards/arm64: Add QEMU Virt KVM support	2022-11-17 11:16:08 +01:00
bindings	dma: dts: gpdma: Add controller attributes to DT	2022-11-23 15:36:31 -05:00
common	…
nios2/intel	flash: nios2_qspi: Add dts binding and nodes for NIOS2 QSPI flash	2022-08-12 08:11:42 -04:00
posix	…
riscv	it8xxx2: generalize ILM support	2022-10-21 20:31:47 +02:00
sparc/gaisler	dts: sparc: Remove label property from devicetrees	2022-07-22 02:51:14 -05:00
x86/intel	board: *_x86: Allow pcie0 to be referenced	2022-11-22 16:24:49 +02:00
xtensa	ace: cavs: dts: Add d-cache and i-cache line size	2022-11-23 15:39:05 -05:00
Kconfig	dts: Include Kconfig.dts as optional source	2022-08-15 11:10:51 -07:00
binding-template.yaml	…